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[AArch64 / Bug Fix] Fixed incorrect BIC implementation and wrong shifters/extenders for logical and arithmetic instructions (fixes #40474) (fixes #40475)

J. Gareth "Kit" Moreton requested to merge CuriousKit/optimisations:a64-bic-fault into main

Summary

This merge request fixes a number of problems with the compiler's interpretation of inline assembly on AArch64:

  • The compiler expects only 2 operands for the BIC instruction when it actually needs to take 3 (issue #40474 (closed)).
  • The compiler permitted extender mnemonics (e.g. UXTB) for NEG, AND, and TST when they are actually invalid (would case an assembler error) (issue #40475 (closed)).
  • The compiler only allowed shift amounts between 0 and 4 instead of the fully supported range of 0 to 31 for 32-bit registers and 0 to 63 for 64-bit registers (issue #40475 (closed)).
  • The compiler didn't allow the shifter mnemonic ROR for logical instructions (AArch64 doesn't support ROR for arithmetic operations, but does for logical operations) (issue #40475 (closed)).

System

  • Operating system: Linux (Raspberry Pi OS)
  • Processor architecture: AArch64
  • Device: Raspberry Pi

What is the current bug behavior?

There are a number of non-conformance issues in AArch64 inline assembly (see Summary above).

What is the behavior after applying this patch?

All of the above should be corrected and fully conforming.

Relevant logs and/or screenshots

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