[x86 / Refactor] Fixed truncated debug comments for And2Btr, Or2Bts, Test2Bt and Xor2Btc

Summary

This merge request fixes the truncating of values in the debug comments (enabled with DEBUG_AOPTCPU) for the And2Btr, Or2Bts, Test2Bt and Xor2Btc peephole optimisations.

System

• Processor architecture: i386, x86_64

What is the current bug behavior?

For And2Btr, Or2Bts, Test2Bt and Xor2Btc, if the input value is greater than 255, the printed value only shows the 2 rightmost digits (often resulting in 0x00).

What is the behavior after applying this patch?

Input values greater than 255 now display anough hexadecimal digits to represent the number correctly and concisely.

Additional notes

• A new debug function, debug_hexstr, takes a TCGInt input and outputs 0x followed by 2, 4, 6, 8 or 16 hexadecimal digits, depending on how many are required to display the whole number in the fewest digits possible from the given set.
• For consistency, $ signs are now also present in front of the output values in the comments.
• No actual code changes occur, and if DEBUG_AOPTCPU is not defined, debug_hexstr just outputs an empty string.

Relevant logs and/or screenshots

In aasmcpu (i386-win32, -O4) - before:

	...
.Lj508:
	# Register eax allocated
	movl	(%esi),%eax
	andl	$536870880,%eax
# Peephole Optimization: Changed OR $0x00 to BTS 13 to shrink instruction size (Or2Bts)
	btsl	$13,%eax
	...

After:

	...
.Lj508:
	# Register eax allocated
	movl	(%esi),%eax
	andl	$536870880,%eax
# Peephole Optimization: Changed OR $0x2000 to BTS $13 to shrink instruction size (Or2Bts)
	btsl	$13,%eax
	...

Also in aasmcpu - before:

	...
.Lj2136:
	...
# Peephole Optimization: Changed XOR $0x00 to BTC 29 to shrink instruction size (Xor2Btc)
	btcl	$29,%eax
	...

After:

	...
.Lj2136:
	...
# Peephole Optimization: Changed XOR $0x20000000 to BTC $29 to shrink instruction size (Xor2Btc)
	btcl	$29,%eax
	...

In advancedipc - before:

	...
.Lj207:
	...
# Peephole Optimization: Changed AND (not $0xFF) to BTR 31 to shrink instruction size (And2Btr)
	btrl	$31,%ebx
	...

After:

	...
.Lj207:
	...
# Peephole Optimization: Changed AND (not $0x7FFFFFFF) to BTR $31 to shrink instruction size (And2Btr)
	btrl	$31,%ebx
	...

In aoptobj - before:

	...
.Lj321:
	...
# Peephole Optimization: Changed OR $0x00 to BTS 18 to shrink instruction size (Or2Bts)
	btsl	$18,%eax

After:

	...
.Lj321:
	...
# Peephole Optimization: Changed OR $0x040000 to BTS $18 to shrink instruction size (Or2Bts)
	btsl	$18,%eax

In app - before:

.Lj256:
	...
# Peephole Optimization: Changed XOR $0x00 to BTC 8 to shrink instruction size (Xor2Btc)
	btcl	$8,%eax

After:

.Lj256:
	...
# Peephole Optimization: Changed XOR $0x0100 to BTC $8 to shrink instruction size (Xor2Btc)
	btcl	$8,%eax

In assemble - before:

	...
# Peephole Optimization: Changed AND (not $0xFF) to BTR 10 to shrink instruction size (And2Btr)
	btrl	$10,%esi
.Lj916:
	# Register eflags allocated
	testb	$64,U_$SYSTEMS_$$_TARGET_INFO+57
	jne	.Lj918
	# Register eflags released
# Peephole Optimization: Changed AND (not $0xFF) to BTR 8 to shrink instruction size (And2Btr)
	btrl	$8,%esi
.Lj918:
	...

After:

	...
# Peephole Optimization: Changed AND (not $0xFFFFFFFFFFFFFBFF) to BTR $10 to shrink instruction size (And2Btr)
	btrl	$10,%esi
.Lj916:
	# Register eflags allocated
	testb	$64,U_$SYSTEMS_$$_TARGET_INFO+57
	jne	.Lj918
	# Register eflags released
# Peephole Optimization: Changed AND (not $0xFFFFFFFFFFFFFEFF) to BTR $8 to shrink instruction size (And2Btr)
	btrl	$8,%esi
.Lj918:
	...

In daemonapp - before:

	...
.Lj340:
# Peephole Optimization: Changed OR $0x00 to BTS 9 to shrink instruction size (Or2Bts)
	btsl	$9,%eax
.Lj339:
	# Register eflags allocated
# Peephole Optimization: Changed TEST $0x00 to BT 8 to shrink instruction size (Test2Bt)
	btl	$8,%edx
	...

After:

	...
.Lj340:
# Peephole Optimization: Changed OR $0x0200 to BTS $9 to shrink instruction size (Or2Bts)
	btsl	$9,%eax
.Lj339:
	# Register eflags allocated
# Peephole Optimization: Changed TEST $0x0100 to BT $8 to shrink instruction size (Test2Bt)
	btl	$8,%edx
	...