This merge request fixes some minor peephole optimisation errors on x86 platforms that, while not yet causing problems, have revealed themselves during more complex development, and may manifest randomly in a contrived example (none of which have been found yet). This request is split into three distinct commits:
- The flags register is now properly tracked throughout the CMOV instructions that are generated by the JccMov2CMov optimisation.
- For CMOV itself, the instruction property flag "Wop2" has been changed to "Mop2" because of the possibility of the register not actually being written to and it retaining its current value. This caused RegUsedAfterInstruction to incorrectly return False if the next immediate instruction was CMOV and may cause an erroneous simplification that would result in the register becoming undefined if CMOV's condition wasn't met.
- For the "MovMovXX2MovXX 1" optimisation, the registers that appear in the reference are now properly tracked.
- Processor architecture: i386, x86_64, possibly i8086
- The CMOV property bug manifested when Pass 2 was run twice, while the "MovMovXX2MovXX 1" manifested when some pass 1 optimisations were run again. The JccMov2CMov flag tracking didn't trigger a bug, but since many peephole optimisations rely on correct register tracking, I want to make sure things are correct.
- There are other reference optimisations where the registers aren't tracked properly. Since the code to do this is virtually identical, I propose writing a new "AllocRefRegsBetween" method in the future to accommodate this.