PCI/PTM: Cache PTM Capability offset
This is a sequence of patches from the pci maintainer branch that address a PCI error seen when thunderbolt is enabled on the P1 and P16 systems that have an Nvidia card. https://lore.kernel.org/lkml/20220909202505.314195-1-helgaas@kernel.org/
Thanks
Mark
Cache the PTM Capability offset instead of searching for it every time we enable/disable PTM or save/restore PTM state. No functional change intended.
Link: https://lore.kernel.org/r/20220909202505.314195-2-helgaas@kernel.org Tested-by: Rajvi Jingar rajvi.jingar@linux.intel.com Signed-off-by: Bjorn Helgaas bhelgaas@google.com Reviewed-by: Kuppuswamy Sathyanarayanan sathyanarayanan.kuppuswamy@linux.intel.com Reviewed-by: Mika Westerberg mika.westerberg@linux.intel.com
Upstream Status: helgaas/pci.git (cherry picked from commit a47126ec)
Needed to address PCI errors seen on boot on P1G5 and P16 Signed-off-by: Mark Pearson mpearson@lenovo.com