Meson DRM/VPU Switch to CCF

As of today, the Meson DRM drivers configures clocks directly in the HHI registers, this doesn't scale well when we want to support DSI for example where the GP0 PLL is used in the clock tree.

HDMI PLL has custom settings for some modes, same for clock paths including specific dividing tree for the HDMI PHY clock input.

First DT should add all the necessary clocks from the whole video clock tree (vclk & vclk2, including all endpoints) and run the clock setup using CCF instead of HHI access.

Secondly, HHI memory zone should be moved to a syscon phandle instead, same for HDMI since PHY is set-up from HHI. Perhaps an hdmi phy under the HHI syscon/simple-mfd would be better, even if no driver would match it, or perhaps take the opportunity to move it as a standalone PHY driver like Xdarlight did for Meson8. Probably HDMI2 modes would be tricky to handle and would require some new phy defines/struct to be added.

For now, DSI is introduced using CCF but with all the corresponding clock tree (GP0 PLL and VCLK2 chain connected to ENCL) statically set in DT, when the whole clock setup is switched to CCF, the VPU driver would set the vclk/clk2 tree to be used by DSI instead of using static DT tree setup.

The legacy DT will need to still be working, so all current code handling clocks in HHI would need to remain.