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Commit 729aab0b authored by Arnaud Ferraris's avatar Arnaud Ferraris
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riscv: fix build with newer GCC

Backported from u-boot mainline.
parent f1d959f0
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......@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
CMODEL = medany
endif
ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
# Newer binutils versions default to ISA spec version 20191213 which moves some
# instructions from the I extension to the Zicsr and Zifencei extensions.
toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
ifeq ($(toolchain-need-zicsr-zifencei),y)
RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
endif
ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
-mcmodel=$(CMODEL)
PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
......
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