Reference functions/types/subtypes outside scope, similar to external names in VHDL 2008
One thing I run into during verification quite often is the need to reference functions in an entity from a testbench or BFM. When verifying designs that do not use VHDL2008, functions and types tend to get defined in the architecture of an entity and it can sometimes be useful to reference these. I am proposing that it should be possible to reference these similar to that of VHDL2008 external names for constants/signals/variables.