Conditional Ports using generics and parameters discriminant format (based on Ada)
Is your capability/feature request related to a problem?
Need conditional port and parameter generation on instance by instance basis
Describe the solution you'd like
Note for the discriminant format, so far I have only used the case format as that is what Ada has. It seems prudent and a nice simplification here if we also added an if syntax.
Discriminants on an Entity Interface
Ada supports case for their discriminant format. I suspect we may want also support if, just because of cases like this. It would look like:
entity FIFO_Core is
generic(
g_DATA_WIDTH : positive := 32;
g_FIFO_DEPTH : positive := 256;
g_HAS_ALMOST_FLAGS : boolean := FALSE
);
port(
clk : in std_ulogic;
reset_n : in std_ulogic;
wr_en : in std_ulogic;
wr_data : in std_ulogic_vector(g_DATA_WIDTH-1 downto 0);
rd_en : in std_ulogic;
rd_data : out std_ulogic_vector(g_DATA_WIDTH-1 downto 0);
empty : out std_ulogic;
full : out std_ulogic;
case g_HAS_ALMOST_FLAGS is
when TRUE =>
-- The following ports are only available when g_HAS_ALMOST_FLAGS = TRUE
almost_empty_threshold : in natural range 0 to g_FIFO_DEPTH;
almost_full_threshold : in natural range 0 to g_FIFO_DEPTH;
almost_empty : out std_ulogic;
almost_full : out std_ulogic;
when others =>
end case ;
);
end entity FIFO_Core;
Discriminants on an Subprogram Interface
Since interface lists are ordered, it seems like it would be possible to use either generics or parameters for this application. I choose generics because with VHDL-2019, they can be specified in the subprogram call (appropriate here) and since I made the default value TRUE, you only need to set them to FALSE when you want to turn them off.
If this were done with a parameter, then the parameter would need to be defined before the usage and it would always need to be specified, unless you were using named association.
procedure axi4_to_channel
generic (
constant gHAS_WRITE : boolean := TRUE ;
constant gHAS_READ : boolean := TRUE ;
) ;
parameter (
signal axi4_m2s : in axi4_m2s_t;
signal axi4_s2m : out axi4_s2m_t;
case HasWrite is
when TRUE =>
signal awaddr_if : out aximm_addr_trans_t;
signal awvalid : out std_logic;
signal awready : in std_logic;
signal wdata_if : out aximm_wdata_trans_t;
signal wvalid : out std_logic;
signal wready : in std_logic;
signal bresp_if : in aximm_bresp_trans_t;
signal bvalid : in std_logic;
signal bready : out std_logic;
when others =>
end case ;
case HasRead is
when TRUE =>
signal araddr_if : out aximm_addr_trans_t;
signal arvalid : out std_logic;
signal arready : in std_logic;
signal rdata_if : in aximm_rdata_trans_t;
signal rvalid : in std_logic;
signal rready : out std_logic ;
when others =>
end case ;
);```
# Describe alternatives you've considered
None
# Additional context
Addresses issues raised in #82,
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