Reduce dimensions where possible
The Technology for the first version of the PDK did not use minimal dimension in several places to get the generated standard cell libraries DRC clean. In future we want to reduce these dimensions. The dimensions that are not minimal have a TODO commnent in the pdkmaster.py
and stdcell.py
file.
The reductions likely only possible after related improvements in upstream PDKMaster
or c4m.flexcell
are done.
Changes needed:
-
different l for nmos and pmos transistor in standard cells (for 5V min. l is 0.6µm for NMOS and 0.5µm for PMOS) -
minimum space violation for 'COMP' layer for adjacent transistors. -
minimum gate-implant enclosure vs minimum diffusion-implant enclosure -
several rules allow smaller dimensions for 3.3V devices than for 5V but are using the 5V ones -
...