V

verilog

RISC-Y: RISC-V-Inspired Siple Computer for You

Verible build container.

Cocotb Demo Project and Its CI/CD Example

Projects done and as hobbist during the studies on Electromobilty @ WUT

PyTCL allows control EDA tools directly from Python that use TCL.

HACK CPU from course nand2tetris written in verilog with vga and ps/2 keyboard.

Implementation of Intel8080 cpu written in verilog running spaceinvaders.

Running legacy Xilinx ISE FPGA software on a MacOS system (including Apple Silicon) using Docker.

A basic RV32I core for practice.

The soft core for the Ice Sea VR headset. Designed to be run on the FPGA of the headset mainboard

My own Single-Borard-Computer projects.

Set of simple modules to communicate via SPI protocol.

This project is about building Hack on real hardware as proposed in chapter 13 of the course nand2tetris using only FOSS, free and open source hard- and software.

Collection of utility modules written in Verilog

Set of simple modules to communicate via UART

Collection of simple interfaces for Digilent Pmods

Interface module for MCP4725 DAC

Encoder and decoder modules for infrared receivers, transmitters and remotes