V

VHDL

A library to represent and manipulate Hardware Description Language (HDL) block designs in Python

https://hdl-block-design.readthedocs.io/en/latest/

Project for the bachelor course Design of Computer Systems at BUT FIT. Creating a VHDL processor with a simple instruction set similar to BrainF*ck, using the Brainlove extension.

Project for the bachelor's course Digital Systems Design at BUT FIT. The aim of the project was to create UART communications using VHDL and analyze the simulations.

Generic UART with parity

Nand2Tetris implementation in VHDL

PyTCL allows control EDA tools directly from Python that use TCL.

Estrin's scheme is an algorithm for numerical evaluation of polynomials.

Z80 @10 MHz PoC for Altera Cyclone II and Cyclone IV (DE0-Nano board) FPGAs

VHDL generator for Gowin pROM IP Core

MO-ALU Logic Design using VHDL & Deeds

This is a small project to display the message ‘Hello World’ on a serial terminal using the UART communication of the Basys3 board.

Running legacy Xilinx ISE FPGA software on a MacOS system (including Apple Silicon) using Docker.

A simple VHDL project to monitor a serial port for ongoing communication.

Project templates and materials for the VHDL Piano assignment.

This is a Tic-Tac-Toe game that is written in VHDL.

Simple SDRAM test for Cyclone FPGA in VHDL

VHDL examples for use in D-H-EHE-SOC class

A Free HardWare Design of minimalist RISC 8-bit processor core for your System-on-Chip. See ygrec8.com

A synchronous protocol for accessing an asynchronous digital Design-Under-Test (JTAG sans the hassles)