new with svd2rust-0.14.0

README.md

@@ -2,7 +2,7 @@
     
 generated from using an svd from https://github.com/posborne/cmsis-svd
 
-`svd2rust -i ./data/STMicro/STM32F030.svd | rustfmt | tee lib.rs`
+`svd2rust -i ./data/STM32F030.svd | rustfmt | tee lib.rs`
 
 then moved lib.rs into src/lib.rs
 

build.rs

+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x"))
+            .unwrap()
+            .write_all(include_bytes!("device.x"))
+            .unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

device.x

+PROVIDE(WWDG = DefaultHandler);
+PROVIDE(PVD = DefaultHandler);
+PROVIDE(RCC_CRS = DefaultHandler);
+PROVIDE(EXTI0_1 = DefaultHandler);
+PROVIDE(EXTI2_3 = DefaultHandler);
+PROVIDE(EXTI4_15 = DefaultHandler);
+PROVIDE(DMA_CH1 = DefaultHandler);
+PROVIDE(DMA_CH2_3 = DefaultHandler);
+PROVIDE(DMA_CH4_5_6_7 = DefaultHandler);
+PROVIDE(ADC_COMP = DefaultHandler);
+PROVIDE(TIM1_BRK_UP_TRG_COM = DefaultHandler);
+PROVIDE(TIM1_CC = DefaultHandler);
+PROVIDE(TIM2 = DefaultHandler);
+PROVIDE(TIM3 = DefaultHandler);
+PROVIDE(TIM6_DAC = DefaultHandler);
+PROVIDE(TIM7 = DefaultHandler);
+PROVIDE(TIM14 = DefaultHandler);
+PROVIDE(I2C1 = DefaultHandler);
+PROVIDE(I2C2 = DefaultHandler);
+PROVIDE(SPI1 = DefaultHandler);
+PROVIDE(SPI2 = DefaultHandler);
+PROVIDE(USART1 = DefaultHandler);
+PROVIDE(USART2 = DefaultHandler);
+PROVIDE(USART3_4 = DefaultHandler);
+

src/adc.rs

+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - interrupt and status register"]
+    pub isr: ISR,
+    #[doc = "0x04 - interrupt enable register"]
+    pub ier: IER,
+    #[doc = "0x08 - control register"]
+    pub cr: CR,
+    #[doc = "0x0c - configuration register 1"]
+    pub cfgr1: CFGR1,
+    #[doc = "0x10 - configuration register 2"]
+    pub cfgr2: CFGR2,
+    #[doc = "0x14 - sampling time register"]
+    pub smpr: SMPR,
+    _reserved0: [u8; 8usize],
+    #[doc = "0x20 - watchdog threshold register"]
+    pub tr: TR,
+    _reserved1: [u8; 4usize],
+    #[doc = "0x28 - channel selection register"]
+    pub chselr: CHSELR,
+    _reserved2: [u8; 20usize],
+    #[doc = "0x40 - data register"]
+    pub dr: DR,
+    _reserved3: [u8; 708usize],
+    #[doc = "0x308 - common configuration register"]
+    pub ccr: CCR,
+}
+#[doc = "interrupt and status register"]
+pub struct ISR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "interrupt and status register"]
+pub mod isr;
+#[doc = "interrupt enable register"]
+pub struct IER {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "interrupt enable register"]
+pub mod ier;
+#[doc = "control register"]
+pub struct CR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "control register"]
+pub mod cr;
+#[doc = "configuration register 1"]
+pub struct CFGR1 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "configuration register 1"]
+pub mod cfgr1;
+#[doc = "configuration register 2"]
+pub struct CFGR2 {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "configuration register 2"]
+pub mod cfgr2;
+#[doc = "sampling time register"]
+pub struct SMPR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "sampling time register"]
+pub mod smpr;
+#[doc = "watchdog threshold register"]
+pub struct TR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "watchdog threshold register"]
+pub mod tr;
+#[doc = "channel selection register"]
+pub struct CHSELR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "channel selection register"]
+pub mod chselr;
+#[doc = "data register"]
+pub struct DR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "data register"]
+pub mod dr;
+#[doc = "common configuration register"]
+pub struct CCR {
+    register: ::vcell::VolatileCell<u32>,
+}
+#[doc = "common configuration register"]
+pub mod ccr;

src/adc/ccr.rs

+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CCR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VBATENR {
+    bits: bool,
+}
+impl VBATENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TSENR {
+    bits: bool,
+}
+impl TSENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VREFENR {
+    bits: bool,
+}
+impl VREFENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VBATENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VBATENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TSENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TSENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 23;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VREFENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VREFENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 22;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 24 - VBAT enable"]
+    #[inline]
+    pub fn vbaten(&self) -> VBATENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        VBATENR { bits }
+    }
+    #[doc = "Bit 23 - Temperature sensor enable"]
+    #[inline]
+    pub fn tsen(&self) -> TSENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 23;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        TSENR { bits }
+    }
+    #[doc = "Bit 22 - Temperature sensor and VREFINT enable"]
+    #[inline]
+    pub fn vrefen(&self) -> VREFENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 22;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        VREFENR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 24 - VBAT enable"]
+    #[inline]
+    pub fn vbaten(&mut self) -> _VBATENW {
+        _VBATENW { w: self }
+    }
+    #[doc = "Bit 23 - Temperature sensor enable"]
+    #[inline]
+    pub fn tsen(&mut self) -> _TSENW {
+        _TSENW { w: self }
+    }
+    #[doc = "Bit 22 - Temperature sensor and VREFINT enable"]
+    #[inline]
+    pub fn vrefen(&mut self) -> _VREFENW {
+        _VREFENW { w: self }
+    }
+}

src/adc/cfgr2.rs

+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CFGR2 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R {
+            bits: self.register.get(),
+        }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct JITOFF_D4R {
+    bits: bool,
+}
+impl JITOFF_D4R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct JITOFF_D2R {
+    bits: bool,
+}
+impl JITOFF_D2R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _JITOFF_D4W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _JITOFF_D4W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 31;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _JITOFF_D2W<'a> {
+    w: &'a mut W,
+}
+impl<'a> _JITOFF_D2W<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 30;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 31 - JITOFF_D4"]
+    #[inline]
+    pub fn jitoff_d4(&self) -> JITOFF_D4R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 31;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        JITOFF_D4R { bits }
+    }
+    #[doc = "Bit 30 - JITOFF_D2"]
+    #[inline]
+    pub fn jitoff_d2(&self) -> JITOFF_D2R {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 30;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        JITOFF_D2R { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 32768 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 31 - JITOFF_D4"]
+    #[inline]
+    pub fn jitoff_d4(&mut self) -> _JITOFF_D4W {
+        _JITOFF_D4W { w: self }
+    }
+    #[doc = "Bit 30 - JITOFF_D2"]
+    #[inline]
+    pub fn jitoff_d2(&mut self) -> _JITOFF_D2W {
+        _JITOFF_D2W { w: self }
+    }
+}

src/adc/cr.rs

+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where