...
 
Commits (20)
......@@ -143,8 +143,20 @@ M: Simon Glass <sjg@chromium.org>
M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
S: Maintained
T: git git://git.denx.de/u-boot-rockchip.git
F: arch/arm/include/asm/arch-rockchip/
F: arch/arm/mach-rockchip/
F: board/rockchip/
F: drivers/clk/rockchip/
F: drivers/gpio/rk_gpio.c
F: drivers/misc/rockchip-efuse.c
F: drivers/pinctrl/rockchip/
F: drivers/ram/rockchip/
F: drivers/sysreset/sysreset_rockchip.c
F: tools/rkcommon.c
F: tools/rkcommon.h
F: tools/rkimage.c
F: tools/rksd.c
F: tools/rkspi.c
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>
......
......@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
rk3128-evb.dtb \
rk3188-radxarock.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
......
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "rk3128.dtsi"
/ {
model = "Rockchip RK3128 Evaluation board";
compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
chosen {
stdout-path = &uart2;
};
vcc5v0_otg: vcc5v0-otg-drv {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_otg";
gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_host: vcc5v0-host-drv {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&i2c1 {
status = "okay";
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
&u2phy {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&usb_host_ehci {
status = "okay";
};
&usb_host_ohci {
status = "okay";
};
&usb_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&emmc {
fifo-mode;
status = "okay";
};
&pinctrl {
usb_otg {
otg_vbus_drv: host-vbus-drv {
rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_host {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
This diff is collapsed.
......@@ -16,6 +16,7 @@
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
};
chosen {
......@@ -544,12 +545,17 @@
&dwc3_typec1 {
status = "okay";
tsd,usb-port-power = "usbhub_enable";
};
&vopb {
status = "okay";
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
......
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_CRU_RK3128_H
#define _ASM_ARCH_CRU_RK3128_H
#include <common.h>
#define MHz 1000000
#define OSC_HZ (24 * MHz)
#define APLL_HZ (600 * MHz)
#define GPLL_HZ (594 * MHz)
#define CORE_PERI_HZ 150000000
#define CORE_ACLK_HZ 300000000
#define BUS_ACLK_HZ 148500000
#define BUS_HCLK_HZ 148500000
#define BUS_PCLK_HZ 74250000
#define PERI_ACLK_HZ 148500000
#define PERI_HCLK_HZ 148500000
#define PERI_PCLK_HZ 74250000
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3128_clk_priv {
struct rk3128_cru *cru;
};
struct rk3128_cru {
struct rk3128_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
} pll[4];
unsigned int cru_mode_con;
unsigned int cru_clksel_con[35];
unsigned int cru_clkgate_con[11];
unsigned int reserved;
unsigned int cru_glb_srst_fst_value;
unsigned int cru_glb_srst_snd_value;
unsigned int reserved1[2];
unsigned int cru_softrst_con[9];
unsigned int cru_misc_con;
unsigned int reserved2[2];
unsigned int cru_glb_cnt_th;
unsigned int reserved3[3];
unsigned int cru_glb_rst_st;
unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
unsigned int cru_sdmmc_con[2];
unsigned int cru_sdio_con[2];
unsigned int reserved5[2];
unsigned int cru_emmc_con[2];
unsigned int reserved6[4];
unsigned int cru_pll_prg_en;
};
check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
struct pll_div {
u32 refdiv;
u32 fbdiv;
u32 postdiv1;
u32 postdiv2;
u32 frac;
};
enum {
/* PLLCON0*/
PLL_POSTDIV1_SHIFT = 12,
PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
PLL_FBDIV_SHIFT = 0,
PLL_FBDIV_MASK = 0xfff,
/* PLLCON1 */
PLL_RST_SHIFT = 14,
PLL_PD_SHIFT = 13,
PLL_PD_MASK = 1 << PLL_PD_SHIFT,
PLL_DSMPD_SHIFT = 12,
PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
PLL_LOCK_STATUS_SHIFT = 10,
PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
PLL_POSTDIV2_SHIFT = 6,
PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
PLL_REFDIV_SHIFT = 0,
PLL_REFDIV_MASK = 0x3f,
/* CRU_MODE */
GPLL_MODE_SHIFT = 12,
GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
GPLL_MODE_SLOW = 0,
GPLL_MODE_NORM,
GPLL_MODE_DEEP,
CPLL_MODE_SHIFT = 8,
CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
CPLL_MODE_SLOW = 0,
CPLL_MODE_NORM,
DPLL_MODE_SHIFT = 4,
DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
DPLL_MODE_SLOW = 0,
DPLL_MODE_NORM,
APLL_MODE_SHIFT = 0,
APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
APLL_MODE_SLOW = 0,
APLL_MODE_NORM,
/* CRU_CLK_SEL0_CON */
BUS_ACLK_PLL_SEL_SHIFT = 14,
BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
BUS_ACLK_PLL_SEL_CPLL = 0,
BUS_ACLK_PLL_SEL_GPLL,
BUS_ACLK_PLL_SEL_GPLL_DIV2,
BUS_ACLK_PLL_SEL_GPLL_DIV3,
BUS_ACLK_DIV_SHIFT = 8,
BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
CORE_CLK_PLL_SEL_SHIFT = 7,
CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
CORE_CLK_PLL_SEL_APLL = 0,
CORE_CLK_PLL_SEL_GPLL_DIV2,
CORE_DIV_CON_SHIFT = 0,
CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
/* CRU_CLK_SEL1_CON */
BUS_PCLK_DIV_SHIFT = 12,
BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
BUS_HCLK_DIV_SHIFT = 8,
BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
CORE_ACLK_DIV_SHIFT = 4,
CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
CORE_PERI_DIV_SHIFT = 0,
CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
/* CRU_CLK_SEL2_CON */
NANDC_PLL_SEL_SHIFT = 14,
NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT,
NANDC_PLL_SEL_CPLL = 0,
NANDC_PLL_SEL_GPLL,
NANDC_CLK_DIV_SHIFT = 8,
NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT,
PVTM_CLK_DIV_SHIFT = 0,
PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT,
/* CRU_CLKSEL10_CON */
PERI_PLL_SEL_SHIFT = 14,
PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT,
PERI_PLL_APLL = 0,
PERI_PLL_DPLL,
PERI_PLL_GPLL,
PERI_PCLK_DIV_SHIFT = 12,
PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
PERI_HCLK_DIV_SHIFT = 8,
PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
PERI_ACLK_DIV_SHIFT = 0,
PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
/* CRU_CLKSEL11_CON */
MMC0_PLL_SHIFT = 6,
MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
MMC0_SEL_APLL = 0,
MMC0_SEL_GPLL,
MMC0_SEL_GPLL_DIV2,
MMC0_SEL_24M,
MMC0_DIV_SHIFT = 0,
MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
/* CRU_CLKSEL12_CON */
EMMC_PLL_SHIFT = 14,
EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
EMMC_SEL_APLL = 0,
EMMC_SEL_GPLL,
EMMC_SEL_GPLL_DIV2,
EMMC_SEL_24M,
EMMC_DIV_SHIFT = 8,
EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
/* CLKSEL_CON24 */
SARADC_DIV_CON_SHIFT = 8,
SARADC_DIV_CON_MASK = GENMASK(15, 8),
SARADC_DIV_CON_WIDTH = 8,
/* CRU_CLKSEL27_CON*/
DCLK_VOP_SEL_SHIFT = 0,
DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
DCLK_VOP_PLL_SEL_CPLL = 0,
DCLK_VOP_DIV_CON_SHIFT = 8,
DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
/* CRU_CLKSEL31_CON */
VIO0_PLL_SHIFT = 5,
VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT,
VI00_SEL_CPLL = 0,
VIO0_SEL_GPLL,
VIO0_DIV_SHIFT = 0,
VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT,
VIO1_PLL_SHIFT = 13,
VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT,
VI01_SEL_CPLL = 0,
VIO1_SEL_GPLL,
VIO1_DIV_SHIFT = 8,
VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT,
/* CRU_SOFTRST5_CON */
DDRCTRL_PSRST_SHIFT = 11,
DDRCTRL_SRST_SHIFT = 10,
DDRPHY_PSRST_SHIFT = 9,
DDRPHY_SRST_SHIFT = 8,
};
#endif
This diff is collapsed.
......@@ -11,6 +11,15 @@ config ROCKCHIP_RK3036
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
config ROCKCHIP_RK3128
bool "Support Rockchip RK3128"
select CPU_V7
help
The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7
......@@ -211,6 +220,7 @@ config SPL_MMC_SUPPORT
default y if !SPL_ROCKCHIP_BACK_TO_BROM
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3128/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk322x/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
......
......@@ -30,6 +30,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-y += boot_mode.o
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
......@@ -43,6 +44,7 @@ obj-y += rk_timer.o
endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
endif
......
......@@ -34,10 +34,11 @@ struct rk3036_sdram_priv {
struct rk3036_ddr_config ddr_config;
};
/* use integer mode, 396MHz dpll setting
/*
* use integer mode, dpll output 792MHz and ddr get 396MHz
* refdiv, fbdiv, postdiv1, postdiv2
*/
const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
/* 396Mhz ddr timing */
const struct rk3036_ddr_timing ddr_timing = {0x18c,
......@@ -329,29 +330,26 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
struct rk3036_pll *pll = &priv->cru->pll[1];
/* pll enter slow-mode */
rk_clrsetreg(&priv->cru->cru_mode_con,
DPLL_MODE_MASK << DPLL_MODE_SHIFT,
rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
/* use integer mode */
rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_clrsetreg(&pll->con0,
PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
(dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
dpll_init_cfg.fbdiv);
rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
(dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
(dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
/* waiting for pll lock */
while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
rockchip_udelay(1);
/* PLL enter normal-mode */
rk_clrsetreg(&priv->cru->cru_mode_con,
DPLL_MODE_MASK << DPLL_MODE_SHIFT,
rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
DPLL_MODE_NORM << DPLL_MODE_SHIFT);
}
......
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <ram.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <asm/arch/grf_rk3128.h>
#include <asm/arch/boot_mode.h>
#include <asm/arch/timer.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
__weak int rk_board_late_init(void)
{
return 0;
}
int board_late_init(void)
{
setup_boot_mode();
return rk_board_late_init();
}
int board_init(void)
{
int ret = 0;
rockchip_timer_init();
ret = regulators_enable_boot_on(false);
if (ret) {
debug("%s: Cannot enable boot on regulator\n", __func__);
return ret;
}
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0xe00000;
gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ gd->ram_size - gd->bd->bi_dram[1].start;
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif
#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
#include <usb.h>
#include <usb/dwc2_udc.h>
static struct dwc2_plat_otg_data rk3128_otg_data = {
.rx_fifo_sz = 512,
.np_tx_fifo_sz = 16,
.tx_fifo_sz = 128,
};
int board_usb_init(int index, enum usb_init_type init)
{
int node;
const char *mode;
bool matched = false;
const void *blob = gd->fdt_blob;
/* find the usb_otg node */
node = fdt_node_offset_by_compatible(blob, -1,
"rockchip,rk3128-usb");
while (node > 0) {
mode = fdt_getprop(blob, node, "dr_mode", NULL);
if (mode && strcmp(mode, "otg") == 0) {
matched = true;
break;
}
node = fdt_node_offset_by_compatible(blob, node,
"rockchip,rk3128-usb");
}
if (!matched) {
debug("Not found usb_otg device\n");
return -ENODEV;
}
rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
return dwc2_udc_probe(&rk3128_otg_data);
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
return 0;
}
#endif
#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
int fb_set_reboot_flag(void)
{
struct rk3128_grf *grf;
printf("Setting reboot to fastboot flag ...\n");
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
/* Set boot mode to fastboot */
writel(BOOT_FASTBOOT, &grf->os_reg[0]);
return 0;
}
#endif
if ROCKCHIP_RK3128
choice
prompt "RK3128 board select"
config TARGET_EVB_RK3128
bool "RK3128 evaluation board"
select BOARD_LATE_INIT
help
RK3128evb is a evaluation board for Rockchip rk3128,
with full function and phisical connectors support like
usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
endchoice
config SYS_SOC
default "rockchip"
config SYS_MALLOC_F_LEN
default 0x0800
source "board/rockchip/evb_rk3128/Kconfig"
endif
#
# (C) Copyright 2017 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += rk3128.o
obj-y += syscon_rk3128.o
obj-y += clk_rk3128.o
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3128.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3128_cru), devp);
}
void *rockchip_get_cru(void)
{
struct rk3128_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
int arch_cpu_init(void)
{
/* We do some SoC one time setting here. */
return 0;
}
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch/clock.h>
static const struct udevice_id rk3128_syscon_ids[] = {
{ .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF },
{ }
};
U_BOOT_DRIVER(syscon_rk3128) = {
.name = "rk3128_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3128_syscon_ids,
};
if TARGET_EVB_RK3128
config SYS_BOARD
default "evb_rk3128"
config SYS_VENDOR
default "rockchip"
config SYS_CONFIG_NAME
default "evb_rk3128"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
EVB-RK3128
M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
F: board/rockchip/evb_rk3128
F: include/configs/evb_rk3128.h
F: configs/evb-rk3128_defconfig
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += evk-rk3128.o
......@@ -3,12 +3,11 @@ Here is the step-by-step to boot U-Boot on rv1108 evb.
Get ddr init binary
==============================================================================
> git clone https://github.com/rockchip-linux/rkbin.git
> dd if=./rkbin/rv1x/rv1108ddr.bin of=ddr.bin bs=4 skip=1
Compile U-Boot
===========================
> make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig all
> ./tools/mkimage -n rv1108 -T rksd -d ddr.bin spl.bin
> ./tools/mkimage -n rv1108 -T rksd -d ../rkbin/rv1x/rv1108ddr_v1.00.bin spl.bin
> cat spl.bin u-boot.bin > u-boot.img
Flash the image by rkdeveloptool
......@@ -16,7 +15,7 @@ Flash the image by rkdeveloptool
rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git
Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
> rkdeveloptool db ./rkbin/rv1x/RV1108_usb_boot.bin
> rkdeveloptool db ./rkbin/rv1x/rv1108usbboot_v1.00.bin
> rkdeveloptool wl 0x40 u-boot.img
> rkdeveloptool RD
......
......@@ -7,12 +7,16 @@
#include <common.h>
#include <dm.h>
#include <misc.h>
#include <spl.h>
#include <usb.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
#include <asm/gpio.h>
#include <asm/setup.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3399.h>
#include <asm/arch/periph.h>
#include <power/regulator.h>
#include <spl.h>
#include <u-boot/sha256.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -32,9 +36,50 @@ int board_init(void)
return 0;
}
static void rk3399_force_power_on_reset(void)
{
ofnode node;
struct gpio_desc sysreset_gpio;
debug("%s: trying to force a power-on reset\n", __func__);
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
debug("%s: no /config node?\n", __func__);
return;
}
if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
&sysreset_gpio, GPIOD_IS_OUT)) {
debug("%s: could not find a /config/sysreset-gpio\n", __func__);
return;
}
dm_gpio_set_value(&sysreset_gpio, 1);
}
void spl_board_init(void)
{
int ret;
struct rk3399_cru *cru = rockchip_get_cru();
/*
* The RK3399 resets only 'almost all logic' (see also in the TRM
* "3.9.4 Global software reset"), when issuing a software reset.
* This may cause issues during boot-up for some configurations of
* the application software stack.
*
* To work around this, we test whether the last reset reason was
* a power-on reset and (if not) issue an overtemp-reset to reset
* the entire module.
*
* While this was previously fixed by modifying the various places
* that could generate a software reset (e.g. U-Boot's sysreset
* driver, the ATF or Linux), we now have it here to ensure that
* we no longer have to track this through the various components.
*/
if (cru->glb_rst_st != 0)
rk3399_force_power_on_reset();
/*
* Turning the eMMC and SPI back on (if disabled via the Qseven
......@@ -158,3 +203,70 @@ void get_board_serial(struct tag_serialnr *serialnr)
serialnr->low = (u32)(serial & 0xffffffff);
}
#endif
/**
* Switch power at an external regulator (for our root hub).
*
* @param ctrl pointer to the xHCI controller
* @param port port number as in the control message (one-based)
* @param enable boolean indicating whether to enable or disable power
* @return returns 0 on success, an error-code on failure
*/
static int board_usb_port_power_set(struct udevice *dev, int port,
bool enable)
{
#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_REGULATOR)
/* We start counting ports at 0, while USB counts from 1. */
int index = port - 1;
const char *regname = NULL;
struct udevice *regulator;
const char *prop = "tsd,usb-port-power";
int ret;
debug("%s: ctrl '%s' port %d enable %s\n", __func__,
dev_read_name(dev), port, enable ? "true" : "false");
ret = dev_read_string_index(dev, prop, index, &regname);
if (ret < 0) {
debug("%s: ctrl '%s' port %d: no entry in '%s'\n",
__func__, dev_read_name(dev), port, prop);
return ret;
}
ret = regulator_get_by_platname(regname, &regulator);
if (ret) {
debug("%s: ctrl '%s' port %d: could not get regulator '%s'\n",
__func__, dev_read_name(dev), port, regname);
return ret;
}
regulator_set_enable(regulator, enable);
return 0;
#else
return -ENOTSUPP;
#endif
}
void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
{
struct udevice *dev = hub->pusb_dev->dev;
struct udevice *ctrl;
/* We are only interested in our root-hubs */
if (usb_hub_is_root_hub(dev) == false)
return;
ctrl = usb_get_bus(dev);
if (!ctrl) {
debug("%s: could not retrieve ctrl for hub\n", __func__);
return;
}
/*
* To work around an incompatibility between the single-threaded
* USB stack in U-Boot and (a strange low-power mode of) the USB
* hub we have on-module, we need to delay powering on the hub
* until the first time the port is probed.
*/
board_usb_port_power_set(ctrl, port, true);
}
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ROCKCHIP_RK3128=y
CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_FASTBOOT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_CMD_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x60800800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3128=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Rockchip"
CONFIG_G_DNL_VENDOR_NUM=0x2207
CONFIG_G_DNL_PRODUCT_NUM=0x310c
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y
......@@ -46,3 +46,9 @@ u-boot,spl-payload-offset
If present (and SPL is controlled by the device-tree), this allows
to override the CONFIG_SYS_SPI_U_BOOT_OFFS setting using a value
from the device-tree.
sysreset-gpio
If present (and supported by the specific board), indicates a
GPIO that can be set to trigger a system reset. It is assumed
that such a system reset will effect a complete platform reset,
being roughly equivalent to a power-on reset.
#
# Copyright (c) 2016 Google, Inc
# Copyright (c) 2017 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
......
This diff is collapsed.
......@@ -168,6 +168,16 @@ config PINCTRL_ROCKCHIP_RK3036
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_ROCKCHIP_RK3128
bool "Rockchip rk3128 pin control driver"
depends on DM
help
Support pin multiplexing control on Rockchip rk3128 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_ROCKCHIP_RK3188
bool "Rockchip rk3188 pin control driver"
depends on DM
......
#
# Copyright (c) 2015 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
# Copyright (c) 2017 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3128) += pinctrl_rk3128.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
......
/*
* Pinctrl driver for Rockchip 3128 SoCs
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk3128.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;
struct rk3128_pinctrl_priv {
struct rk3128_grf *grf;
};
static void pinctrl_rk3128_i2c_config(struct rk3128_grf *grf, int i2c_id)
{
switch (i2c_id) {
case PERIPH_ID_I2C0:
rk_clrsetreg(&grf->gpio0a_iomux,
GPIO0A1_MASK | GPIO0A0_MASK,
GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
break;
case PERIPH_ID_I2C1:
rk_clrsetreg(&grf->gpio0a_iomux,
GPIO0A3_MASK | GPIO0A2_MASK,
GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
break;
case PERIPH_ID_I2C2:
rk_clrsetreg(&grf->gpio2c_iomux2,
GPIO2C5_MASK | GPIO2C4_MASK,
GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
break;
case PERIPH_ID_I2C3:
rk_clrsetreg(&grf->gpio0a_iomux,
GPIO0A7_MASK | GPIO0A6_MASK,
GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
break;
}
}
static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf *grf, int mmc_id)
{
switch (mmc_id) {
case PERIPH_ID_EMMC:
rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A5_MASK | GPIO2A7_MASK,
GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
break;
case PERIPH_ID_SDCARD:
rk_clrsetreg(&grf->gpio1c_iomux, 0x0fff,
GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
break;
}
}
static int rk3128_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
debug("%s: func=%x, flags=%x\n", __func__, func, flags);
switch (func) {
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
pinctrl_rk3128_i2c_config(priv->grf, func);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
pinctrl_rk3128_sdmmc_config(priv->grf, func);
break;
default:
return -EINVAL;
}
return 0;
}
static int rk3128_pinctrl_get_periph_id(struct udevice *dev,
struct udevice *periph)
{
u32 cell[3];
int ret;
ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
switch (cell[1]) {
case 14:
return PERIPH_ID_SDCARD;
case 16:
return PERIPH_ID_EMMC;
case 20:
return PERIPH_ID_UART0;
case 21:
return PERIPH_ID_UART1;
case 22:
return PERIPH_ID_UART2;
case 23:
return PERIPH_ID_SPI0;
case 24:
return PERIPH_ID_I2C0;
case 25:
return PERIPH_ID_I2C1;
case 26:
return PERIPH_ID_I2C2;
case 27:
return PERIPH_ID_I2C3;
case 30:
return PERIPH_ID_PWM0;
}
return -ENOENT;
}
static int rk3128_pinctrl_set_state_simple(struct udevice *dev,
struct udevice *periph)
{
int func;
func = rk3128_pinctrl_get_periph_id(dev, periph);
if (func < 0)
return func;
return rk3128_pinctrl_request(dev, func, 0);
}
static struct pinctrl_ops rk3128_pinctrl_ops = {
.set_state_simple = rk3128_pinctrl_set_state_simple,
.request = rk3128_pinctrl_request,
.get_periph_id = rk3128_pinctrl_get_periph_id,
};
static int rk3128_pinctrl_probe(struct udevice *dev)
{
struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
debug("%s: grf=%p\n", __func__, priv->grf);
return 0;
}
static const struct udevice_id rk3128_pinctrl_ids[] = {
{ .compatible = "rockchip,rk3128-pinctrl" },
{ }
};
U_BOOT_DRIVER(pinctrl_rk3128) = {
.name = "pinctrl_rk3128",
.id = UCLASS_PINCTRL,
.of_match = rk3128_pinctrl_ids,
.priv_auto_alloc_size = sizeof(struct rk3128_pinctrl_priv),
.ops = &rk3128_pinctrl_ops,
.bind = dm_scan_fdt_dev,
.probe = rk3128_pinctrl_probe,
};
......@@ -5,6 +5,7 @@
#
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
......
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <dm.h>
#include <ram.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk3128.h>
#include <asm/arch/sdram_common.h>
DECLARE_GLOBAL_DATA_PTR;
struct dram_info {
struct ram_info info;
struct rk3128_grf *grf;
};
static int rk3128_dmc_probe(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
debug("%s: grf=%p\n", __func__, priv->grf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[1]);
return 0;
}
static int rk3128_dmc_get_info(struct udevice *dev, struct ram_info *info)
{
struct dram_info *priv = dev_get_priv(dev);
*info = priv->info;
return 0;
}
static struct ram_ops rk3128_dmc_ops = {
.get_info = rk3128_dmc_get_info,
};
static const struct udevice_id rk3128_dmc_ids[] = {
{ .compatible = "rockchip,rk3128-dmc" },
{ }
};
U_BOOT_DRIVER(dmc_rk3128) = {
.name = "rockchip_rk3128_dmc",
.id = UCLASS_RAM,
.of_match = rk3128_dmc_ids,
.ops = &rk3128_dmc_ops,
.probe = rk3128_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
};
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EVB_RK3128_H
#define __EVB_RK3128_H
#include <configs/rk3128_common.h>
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_RK3128_COMMON_H
#define __CONFIG_RK3128_COMMON_H
#include "rockchip-common.h"
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
/* MMC/SD IP block */
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_SUPPORT_VFAT
#define CONFIG_FS_EXT4
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 2
#define SDRAM_MAX_SIZE 0x80000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#ifndef CONFIG_SPL_BUILD
/* usb mass storage */
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x60500000\0" \
"pxefile_addr_r=0x60600000\0" \
"fdt_addr_r=0x61f00000\0" \
"kernel_addr_r=0x62000000\0" \
"ramdisk_addr_r=0x64000000\0"
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
"partitions=" PARTS_DEFAULT \
BOOTENV
#endif
#endif
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_GPLL 3
#define ARMCLK 4
/* sclk gates (special clocks) */
#define SCLK_GPU 64
#define SCLK_SPI 65
#define SCLK_SDMMC 68
#define SCLK_SDIO 69
#define SCLK_EMMC 71
#define SCLK_NANDC 76
#define SCLK_UART0 77
#define SCLK_UART1 78
#define SCLK_UART2 79
#define SCLK_I2S 82
#define SCLK_SPDIF 83
#define SCLK_TIMER0 85
#define SCLK_TIMER1 86
#define SCLK_TIMER2 87
#define SCLK_TIMER3 88
#define SCLK_SARADC 91
#define SCLK_OTGPHY0 93
#define SCLK_LCDC 100
#define SCLK_HDMI 109
#define SCLK_HEVC 111
#define SCLK_I2S_OUT 113
#define SCLK_SDMMC_DRV 114
#define SCLK_SDIO_DRV 115
#define SCLK_EMMC_DRV 117
#define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO_SAMPLE 119
#define SCLK_EMMC_SAMPLE 121
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
#define SCLK_PVTM_VIDEO 125
#define SCLK_MAC 151
#define SCLK_MACREF 152
#define SCLK_SFC 160
#define DCLK_LCDC 190
/* aclk gates */
#define ACLK_DMAC2 194
#define ACLK_VIO0 197
#define ACLK_VIO1 203
#define ACLK_VCODEC 208
#define ACLK_CPU 209
#define ACLK_PERI 210
/* pclk gates */
#define PCLK_SARADC 318
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
#define PCLK_GPIO3 323
#define PCLK_GRF 329
#define PCLK_I2C0 332
#define PCLK_I2C1 333
#define PCLK_I2C2 334
#define PCLK_I2C3 335
#define PCLK_SPI 338
#define PCLK_UART0 341
#define PCLK_UART1 342
#define PCLK_UART2 343
#define PCLK_PWM 350
#define PCLK_TIMER 353
#define PCLK_HDMI 360
#define PCLK_CPU 362
#define PCLK_PERI 363
#define PCLK_DDRUPCTL 364
#define PCLK_WDT 368
/* hclk gates */
#define HCLK_OTG0 449
#define HCLK_OTG1 450
#define HCLK_NANDC 453
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
#define HCLK_I2S 462
#define HCLK_LCDC 465
#define HCLK_ROM 467
#define HCLK_VIO_BUS 472
#define HCLK_VCODEC 476
#define HCLK_CPU 477
#define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_CORE0 0
#define SRST_CORE1 1
#define SRST_CORE0_DBG 4
#define SRST_CORE1_DBG 5
#define SRST_CORE0_POR 8
#define SRST_CORE1_POR 9
#define SRST_L2C 12
#define SRST_TOPDBG 13
#define SRST_STRC_SYS_A 14
#define SRST_PD_CORE_NIU 15
#define SRST_TIMER2 16
#define SRST_CPUSYS_H 17
#define SRST_AHB2APB_H 19
#define SRST_TIMER3 20
#define SRST_INTMEM 21
#define SRST_ROM 22
#define SRST_PERI_NIU 23
#define SRST_I2S 24
#define SRST_DDR_PLL 25
#define SRST_GPU_DLL 26
#define SRST_TIMER0 27
#define SRST_TIMER1 28
#define SRST_CORE_DLL 29
#define SRST_EFUSE_P 30
#define SRST_ACODEC_P 31
#define SRST_GPIO0 32
#define SRST_GPIO1 33
#define SRST_GPIO2 34
#define SRST_UART0 39
#define SRST_UART1 40
#define SRST_UART2 41
#define SRST_I2C0 43
#define SRST_I2C1 44
#define SRST_I2C2 45
#define SRST_SFC 47
#define SRST_PWM0 48
#define SRST_DAP 51
#define SRST_DAP_SYS 52
#define SRST_GRF 55
#define SRST_PERIPHSYS_A 57
#define SRST_PERIPHSYS_H 58
#define SRST_PERIPHSYS_P 59
#define SRST_CPU_PERI 61
#define SRST_EMEM_PERI 62
#define SRST_USB_PERI 63
#define SRST_DMA2 64
#define SRST_MAC 66
#define SRST_NANDC 68
#define SRST_USBOTG0 69
#define SRST_OTGC0 71
#define SRST_USBOTG1 72
#define SRST_OTGC1 74
#define SRST_DDRMSCH 79
#define SRST_MMC0 81
#define SRST_SDIO 82
#define SRST_EMMC 83
#define SRST_SPI0 84
#define SRST_WDT 86
#define SRST_SARADC 87
#define SRST_DDRPHY 88
#define SRST_DDRPHY_P 89
#define SRST_DDRCTRL 90
#define SRST_DDRCTRL_P 91
#define SRST_HDMI_P 96
#define SRST_VIO_BUS_H 99
#define SRST_UTMI0 103
#define SRST_UTMI1 104
#define SRST_USBPOR 105
#define SRST_VCODEC_A 112
#define SRST_VCODEC_H 113
#define SRST_VIO1_A 114
#define SRST_HEVC 115
#define SRST_VCODEC_NIU_A 116
#define SRST_LCDC1_A 117