...
 
Commits (49)
......@@ -133,6 +133,7 @@ F: arch/arm/include/asm/arch-pxa/
ARM RENESAS RMOBILE/R-CAR
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
M: Marek Vasut <marek.vasut+renesas@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-sh.git
F: arch/arm/mach-rmobile/
......
......@@ -258,6 +258,19 @@
marvell,function = "i2c0";
};
nand_pins: nand-pins {
marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
"mpp38", "mpp28", "mpp40", "mpp42",
"mpp35", "mpp36", "mpp25", "mpp30",
"mpp32";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp41";
marvell,function = "nand";
};
mdio_pins: mdio-pins {
marvell,pins = "mpp4", "mpp5";
marvell,function = "ge";
......@@ -545,7 +558,7 @@
};
flash@d0000 {
compatible = "marvell,armada370-nand";
compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
......
......@@ -394,6 +394,7 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
......
......@@ -377,6 +377,7 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
......
......@@ -24,6 +24,15 @@
stdout-path = "serial0:115200n8";
};
cpld {
compatible = "renesas,ulcb-cpld";
status = "okay";
gpio-sck = <&gpio6 8 0>;
gpio-mosi = <&gpio6 7 0>;
gpio-miso = <&gpio6 10 0>;
gpio-sstbz = <&gpio2 3 0>;
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
......@@ -190,6 +199,10 @@
};
};
&i2c_dvfs {
status = "okay";
};
&ohci1 {
status = "okay";
};
......@@ -247,7 +260,7 @@
sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {
......
......@@ -111,10 +111,16 @@
#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
/* BootROM error register (also includes some status infos) */
#if defined(CONFIG_ARMADA_38X)
#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 0
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#else
#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 28
#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART 0x6
#endif
#if defined(CONFIG_ARMADA_375)
/* SAR values for Armada 375 */
......@@ -141,6 +147,7 @@
#define BOOT_DEV_SEL_OFFS 4
#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
#define BOOT_FROM_NAND 0x0A
#define BOOT_FROM_UART 0x28
#define BOOT_FROM_UART_ALT 0x3f
#define BOOT_FROM_SPI 0x32
......
......@@ -26,7 +26,16 @@ static u32 get_boot_device(void)
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
#if defined(CONFIG_ARMADA_38X)
/*
* If the bootrom error register contains any else than zeros
* in the first 8 bits it's an error condition. And in that case
* try to boot from UART.
*/
if (boot_device)
#else
if (boot_device == BOOTROM_ERR_MODE_UART)
#endif
return BOOT_DEVICE_UART;
/*
......@@ -36,6 +45,10 @@ static u32 get_boot_device(void)
boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
switch (boot_device) {
#if defined(CONFIG_ARMADA_38X)
case BOOT_FROM_NAND:
return BOOT_DEVICE_NAND;
#endif
#ifdef CONFIG_SPL_MMC_SUPPORT
case BOOT_FROM_MMC:
case BOOT_FROM_MMC_ALT:
......@@ -119,7 +132,15 @@ void board_init_f(ulong dummy)
* SPL has no chance to receive this information. So we
* need to return to the BootROM to enable this xmodem
* UART download.
*
* If booting from NAND lets let the BootROM load the
* rest of the bootloader.
*/
if (get_boot_device() == BOOT_DEVICE_UART)
return_to_bootrom();
switch (get_boot_device()) {
case BOOT_DEVICE_UART:
#if defined(CONFIG_ARMADA_38X)
case BOOT_DEVICE_NAND:
#endif
return_to_bootrom();
}
}
......@@ -16,7 +16,6 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o
obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
......@@ -8,8 +8,10 @@
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#ifndef CONFIG_RCAR_GEN3
int checkboard(void)
{
printf("Board: %s\n", sysinfo.board_string);
return 0;
}
#endif
......@@ -8,19 +8,20 @@
#include <common.h>
#include <asm/io.h>
#define PRR 0xFF000044
#define PRR_MASK 0x7fff
#define R8A7796_REV_1_0 0x5200
#define R8A7796_REV_1_1 0x5210
static u32 rmobile_get_prr(void);
u32 rmobile_get_cpu_type(void)
{
return (readl(PRR) & 0x00007F00) >> 8;
return (rmobile_get_prr() & 0x00007F00) >> 8;
}
u32 rmobile_get_cpu_rev_integer(void)
{
const u32 prr = readl(PRR);
const u32 prr = rmobile_get_prr();
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
return 1;
......@@ -30,10 +31,62 @@ u32 rmobile_get_cpu_rev_integer(void)
u32 rmobile_get_cpu_rev_fraction(void)
{
const u32 prr = readl(PRR);
const u32 prr = rmobile_get_prr();
if ((prr & PRR_MASK) == R8A7796_REV_1_1)
return 1;
else
return prr & 0x0000000F;
}
#if !CONFIG_IS_ENABLED(DM) || !CONFIG_IS_ENABLED(SYSCON)
static u32 rmobile_get_prr(void)
{
/*
* On RCar/RMobile Gen2 and older systems, the PRR is always
* located at the address below. On newer systems, the PRR
* may be located at different address, but that information
* is obtained from DT. This code will be removed when all
* of the older systems get converted to DM and OF control.
*/
return readl(0xFF000044);
}
#else
#include <dm.h>
#include <syscon.h>
#include <regmap.h>
struct renesas_prr_priv {
fdt_addr_t regs;
};
enum {
PRR_RCAR,
};
static u32 rmobile_get_prr(void)
{
struct regmap *map;
map = syscon_get_regmap_by_driver_data(PRR_RCAR);
if (!map) {
printf("PRR regmap failed!\n");
hang();
}
return readl(map->base);
}
static const struct udevice_id renesas_prr_ids[] = {
{ .compatible = "renesas,prr", .data = PRR_RCAR },
{ }
};
U_BOOT_DRIVER(renesas_prr) = {
.name = "renesas_prr",
.id = UCLASS_SYSCON,
.of_match = renesas_prr_ids,
.flags = DM_FLAG_PRE_RELOC,
};
#endif
......@@ -18,6 +18,9 @@ int arch_cpu_init(void)
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_RCAR_GEN3)
rcar_gen3_memmap_fixup();
#endif
dcache_enable();
}
#endif
......@@ -49,15 +52,15 @@ static const struct {
u16 cpu_type;
u8 cpu_name[10];
} rmobile_cpuinfo[] = {
{ 0x37, "SH73A0" },
{ 0x40, "R8A7740" },
{ 0x45, "R8A7790" },
{ 0x47, "R8A7791" },
{ 0x4A, "R8A7792" },
{ 0x4B, "R8A7793" },
{ 0x4C, "R8A7794" },
{ 0x4F, "R8A7795" },
{ 0x52, "R8A7796" },
{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
{ RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ 0x0, "CPU" },
};
......
......@@ -22,12 +22,6 @@ void r8a7793_pinmux_init(void);
#elif defined(CONFIG_R8A7794)
#include "r8a7794-gpio.h"
void r8a7794_pinmux_init(void);
#elif defined(CONFIG_R8A7795)
#include "r8a7795-gpio.h"
void r8a7795_pinmux_init(void);
#elif defined(CONFIG_R8A7796)
#include "r8a7796-gpio.h"
void r8a7796_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */
This diff is collapsed.
/*
* arch/arm/mach-rmobile/include/mach/r8a7795.h
* This file defines registers and value for r8a7795.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_R8A7795_H
#define __ASM_ARCH_R8A7795_H
#include "rcar-gen3-base.h"
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00640800
#define MSTP1_BITS 0xF3EE9390
#define MSTP2_BITS 0x340FAFDC
#define MSTP3_BITS 0xD80C7CDF
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0x40BFFF46
#define MSTP6_BITS 0xE5FBEECF
#define MSTP7_BITS 0x39FFFF0E
#define MSTP8_BITS 0x01F19FF4
#define MSTP9_BITS 0xFFDFFFFF
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x00000000
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
#endif /* __ASM_ARCH_R8A7795_H */
This diff is collapsed.
/*
* arch/arm/include/asm/arch-rcar_gen3/r8a7796.h
* This file defines registers and value for r8a7796.
*
* Copyright (C) 2016 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_R8A7796_H
#define __ASM_ARCH_R8A7796_H
#include "rcar-gen3-base.h"
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00200000
#define MSTP1_BITS 0xFFFFFFFF
#define MSTP2_BITS 0x340E2FDC
#define MSTP3_BITS 0xFFFFFFDF
#define MSTP4_BITS 0x80000184
#define MSTP5_BITS 0xC3FFFFFF
#define MSTP6_BITS 0xFFFFFFFF
#define MSTP7_BITS 0xFFFFFFFF
#define MSTP8_BITS 0x01F1FFF7
#define MSTP9_BITS 0xFFFFFFFE
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000000B7
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
#endif /* __ASM_ARCH_R8A7796_H */
......@@ -68,12 +68,6 @@
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
/* PFC */
#define PFC_PUEN5 0xE6060414
#define PUEN_SSI_SDATA4 BIT(17)
......
......@@ -16,19 +16,29 @@
#include <asm/arch/r8a7793.h>
#elif defined(CONFIG_R8A7794)
#include <asm/arch/r8a7794.h>
#elif defined(CONFIG_R8A7795)
#include <asm/arch/r8a7795.h>
#elif defined(CONFIG_R8A7796)
#include <asm/arch/r8a7796.h>
#elif defined(CONFIG_RCAR_GEN3)
#include <asm/arch/rcar-gen3-base.h>
#else
#error "SOC Name not defined"
#endif
#endif /* CONFIG_ARCH_RMOBILE */
/* PRR CPU IDs */
#define RMOBILE_CPU_TYPE_SH73A0 0x37
#define RMOBILE_CPU_TYPE_R8A7740 0x40
#define RMOBILE_CPU_TYPE_R8A7790 0x45
#define RMOBILE_CPU_TYPE_R8A7791 0x47
#define RMOBILE_CPU_TYPE_R8A7792 0x4A
#define RMOBILE_CPU_TYPE_R8A7793 0x4B
#define RMOBILE_CPU_TYPE_R8A7794 0x4C
#define RMOBILE_CPU_TYPE_R8A7795 0x4F
#define RMOBILE_CPU_TYPE_R8A7796 0x52
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);
u32 rmobile_get_cpu_rev_integer(void);
u32 rmobile_get_cpu_rev_fraction(void);
void rcar_gen3_memmap_fixup(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RMOBILE_H */
/*
* Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Renesas RCar Gen3 memory map tables
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -27,4 +29,38 @@ static struct mm_region r8a7795_mem_map[] = {
}
};
static struct mm_region r8a7796_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe0000000UL,
.phys = 0xe0000000UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = r8a7795_mem_map;
void rcar_gen3_memmap_fixup(void)
{
u32 cpu_type = rmobile_get_cpu_type();
switch (cpu_type) {
case RMOBILE_CPU_TYPE_R8A7795:
mem_map = r8a7795_mem_map;
break;
case RMOBILE_CPU_TYPE_R8A7796:
mem_map = r8a7796_mem_map;
break;
}
}
/*
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv8/mmu.h>
static struct mm_region r8a7796_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe0000000UL,
.phys = 0xe0000000UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = r8a7796_mem_map;
This diff is collapsed.
This diff is collapsed.
......@@ -34,9 +34,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions
PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64)
LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
# This is used in the top-level Makefile which does not include
# PLATFORM_LDFLAGS
LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined
......
......@@ -143,8 +143,8 @@ const char *cpu_vendor_name(int vendor)
{
const char *name;
name = "<invalid cpu vendor>";
if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
(x86_vendor_name[vendor] != 0))
if (vendor < ARRAY_SIZE(x86_vendor_name) &&
x86_vendor_name[vendor])
name = x86_vendor_name[vendor];
return name;
......
......@@ -18,7 +18,7 @@ if QEMU
config SYS_CAR_ADDR
hex
default 0xd0000
default 0x10000
config SYS_CAR_SIZE
hex
......
......@@ -18,7 +18,6 @@ obj-$(CONFIG_SEABIOS) += coreboot_table.o
obj-y += early_cmos.o
obj-$(CONFIG_EFI) += efi/
obj-y += e820.o
obj-y += gcc.o
obj-y += init_helpers.o
obj-y += interrupts.o
obj-y += lpc-uclass.o
......@@ -49,12 +48,7 @@ endif
obj-$(CONFIG_HAVE_FSP) += fsp/
obj-$(CONFIG_SPL_BUILD) += spl.o
extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a
NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name)
OBJCOPYFLAGS := --prefix-symbols=__normal_
$(obj)/lib.a: $(NORMAL_LIBGCC) FORCE
$(call if_changed,objcopy)
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += div64.o
ifeq ($(CONFIG_$(SPL_)X86_64),)
obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o
......
......@@ -109,7 +109,7 @@ static int boot_prep_linux(bootm_headers_t *images)
}
is_zimage = 1;
#if defined(CONFIG_FIT)
} else if (images->fit_uname_os) {
} else if (images->fit_uname_os && is_zimage) {
ret = fit_image_get_data(images->fit_hdr_os,
images->fit_noffset_os,
(const void **)&data, &len);
......
/*
* This file is copied from the coreboot repository as part of
* the libpayload project:
*
* Copyright 2014 Google Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common.h>
union overlay64 {
u64 longw;
struct {
u32 lower;
u32 higher;
} words;
};
u64 __ashldi3(u64 num, unsigned int shift)
{
union overlay64 output;
output.longw = num;
if (shift >= 32) {
output.words.higher = output.words.lower << (shift - 32);
output.words.lower = 0;
} else {
if (!shift)
return num;
output.words.higher = (output.words.higher << shift) |
(output.words.lower >> (32 - shift));
output.words.lower = output.words.lower << shift;
}
return output.longw;
}
u64 __lshrdi3(u64 num, unsigned int shift)
{
union overlay64 output;
output.longw = num;
if (shift >= 32) {
output.words.lower = output.words.higher >> (shift - 32);
output.words.higher = 0;
} else {
if (!shift)
return num;
output.words.lower = output.words.lower >> shift |
(output.words.higher << (32 - shift));
output.words.higher = output.words.higher >> shift;
}
return output.longw;
}
#define MAX_32BIT_UINT ((((u64)1) << 32) - 1)
static u64 _64bit_divide(u64 dividend, u64 divider, u64 *rem_p)
{
u64 result = 0;
/*
* If divider is zero - let the rest of the system care about the
* exception.
*/
if (!divider)
return 1 / (u32)divider;
/* As an optimization, let's not use 64 bit division unless we must. */
if (dividend <= MAX_32BIT_UINT) {
if (divider > MAX_32BIT_UINT) {
result = 0;
if (rem_p)
*rem_p = divider;
} else {
result = (u32)dividend / (u32)divider;
if (rem_p)
*rem_p = (u32)dividend % (u32)divider;
}
return result;
}
while (divider <= dividend) {
u64 locald = divider;
u64 limit = __lshrdi3(dividend, 1);
int shifts = 0;
while (locald <= limit) {
shifts++;
locald = locald + locald;
}
result |= __ashldi3(1, shifts);
dividend -= locald;
}
if (rem_p)
*rem_p = dividend;
return result;
}
u64 __udivdi3(u64 num, u64 den)
{
return _64bit_divide(num, den, NULL);
}
u64 __umoddi3(u64 num, u64 den)
{
u64 v = 0;
_64bit_divide(num, den, &v);
return v;
}
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifdef __GNUC__
/*
* GCC's libgcc handling is quite broken. While the libgcc functions
* are always regparm(0) the code that calls them uses whatever the
* compiler call specifies. Therefore we need a wrapper around those
* functions. See gcc bug PR41055 for more information.
*/
#define WRAP_LIBGCC_CALL(type, name) \
type __normal_##name(type a, type b) __attribute__((regparm(0))); \
type __wrap_##name(type a, type b); \
type __attribute__((no_instrument_function)) \
__wrap_##name(type a, type b) \
{ return __normal_##name(a, b); }
WRAP_LIBGCC_CALL(long long, __divdi3)
WRAP_LIBGCC_CALL(unsigned long long, __udivdi3)
WRAP_LIBGCC_CALL(long long, __moddi3)
WRAP_LIBGCC_CALL(unsigned long long, __umoddi3)
#endif
......@@ -212,7 +212,7 @@ static struct hws_topology_map board_topology_map_1g = {
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */
0, 0, /* cas_wl cas_l */
HWS_TEMP_NORMAL, /* temperature */
HWS_TIM_2T} }, /* timing (force 2t) */
5, /* Num Of Bus Per Interface*/
......@@ -231,7 +231,7 @@ static struct hws_topology_map board_topology_map_2g = {
BUS_WIDTH_16, /* memory_width */
MEM_8G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */
0, 0, /* cas_wl cas_l */
HWS_TEMP_NORMAL, /* temperature */
HWS_TIM_2T} }, /* timing (force 2t) */
5, /* Num Of Bus Per Interface*/
......
......@@ -68,7 +68,7 @@ static struct hws_topology_map board_topology_map = {
BUS_WIDTH_8, /* memory_width */
MEM_2G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */
0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
......
......@@ -89,7 +89,7 @@ static struct hws_topology_map board_topology_map = {
BUS_WIDTH_8, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */
0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
......
......@@ -52,7 +52,7 @@ static struct hws_topology_map ddr_topology_map = {
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_533, /* frequency */
0, 0, /* cas_l cas_wl */
0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
......
......@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := salvator-x.o ../rcar-common/common.o
obj-y := salvator-x.o
......@@ -79,17 +79,19 @@ int board_early_init_f(void)
int board_init(void)
{
u32 cpu_type = rmobile_get_cpu_type();
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
#if defined(CONFIG_R8A7795)
/* GSX: force power and clock supply */
writel(0x0000001F, SYSC_PWRONCR2);
while (readl(SYSC_PWRSR2) != 0x000003E0)
mdelay(20);
if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
/* GSX: force power and clock supply */
writel(0x0000001F, SYSC_PWRONCR2);
while (readl(SYSC_PWRSR2) != 0x000003E0)
mdelay(20);
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
#endif
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
}
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
......@@ -107,43 +109,19 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->ram_size += PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
fdtdec_setup_memory_banksize();
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RCAR_BOARD_STRING
};
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
......
......@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ulcb.o cpld.o ../rcar-common/common.o
obj-y := ulcb.o cpld.o
......@@ -8,14 +8,12 @@
*/
#include <common.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/gpio.h>
#define SCLK (192 + 8) /* GPIO6 8 */
#define SSTBZ (64 + 3) /* GPIO2 3 */
#define MOSI (192 + 7) /* GPIO6 8 */
#define MISO (192 + 10) /* GPIO6 10 */
#include <asm/io.h>
#include <dm.h>
#include <errno.h>
#include <linux/err.h>
#include <sysreset.h>
#define CPLD_ADDR_MODE 0x00 /* RW */
#define CPLD_ADDR_MUX 0x02 /* RW */
......@@ -23,111 +21,89 @@
#define CPLD_ADDR_RESET 0x80 /* RW */
#define CPLD_ADDR_VERSION 0xFF /* R */
static int cpld_initialized;
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
/* Always valid */
return 1;
}
void spi_cs_activate(struct spi_slave *slave)
{
/* Always active */
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* Always active */
}
void ulcb_softspi_sda(int set)
{
gpio_set_value(MOSI, set);
}
struct renesas_ulcb_sysreset_priv {
struct gpio_desc miso;
struct gpio_desc mosi;
struct gpio_desc sck;
struct gpio_desc sstbz;
};
void ulcb_softspi_scl(int set)
{
gpio_set_value(SCLK, set);
}
unsigned char ulcb_softspi_read(void)
{
return !!gpio_get_value(MISO);
}
static void cpld_rw(u8 write)
{
gpio_set_value(MOSI, write);
gpio_set_value(SSTBZ, 0);
gpio_set_value(SCLK, 1);
gpio_set_value(SCLK, 0);
gpio_set_value(SSTBZ, 1);
}
static u32 cpld_read(u8 addr)
static u32 cpld_read(struct udevice *dev, u8 addr)
{
struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
u32 data = 0;
int i;
spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
cpld_rw(0);
spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END);
return swab32(data);
}
static void cpld_write(u8 addr, u32 data)
{
data = swab32(data);
spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
for (i = 0; i < 8; i++) {
dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */
dm_gpio_set_value(&priv->sck, 1);
addr <<= 1;
dm_gpio_set_value(&priv->sck, 0);
}
spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END);
dm_gpio_set_value(&priv->mosi, 0); /* READ */
dm_gpio_set_value(&priv->sstbz, 0);
dm_gpio_set_value(&priv->sck, 1);
dm_gpio_set_value(&priv->sck, 0);
dm_gpio_set_value(&priv->sstbz, 1);
for (i = 0; i < 32; i++) {
dm_gpio_set_value(&priv->sck, 1);
data <<= 1;
data |= dm_gpio_get_value(&priv->miso); /* MSB first */
dm_gpio_set_value(&priv->sck, 0);
}
cpld_rw(1);
return data;
}
static void cpld_init(void)
static void cpld_write(struct udevice *dev, u8 addr, u32 data)
{
if (cpld_initialized)
return;
/* PULL-UP on MISO line */
setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
gpio_request(SCLK, NULL);
gpio_request(SSTBZ, NULL);
gpio_request(MOSI, NULL);
gpio_request(MISO, NULL);
gpio_direction_output(SCLK, 0);
gpio_direction_output(SSTBZ, 1);
gpio_direction_output(MOSI, 0);
gpio_direction_input(MISO);
struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
int i;
for (i = 0; i < 32; i++) {
dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */
dm_gpio_set_value(&priv->sck, 1);
data <<= 1;
dm_gpio_set_value(&priv->sck, 0);
}
/* Dummy read */
cpld_read(CPLD_ADDR_VERSION);
for (i = 0; i < 8; i++) {
dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */
dm_gpio_set_value(&priv->sck, 1);
addr <<= 1;
dm_gpio_set_value(&priv->sck, 0);
}
cpld_initialized = 1;
dm_gpio_set_value(&priv->mosi, 1); /* WRITE */
dm_gpio_set_value(&priv->sstbz, 0);
dm_gpio_set_value(&priv->sck, 1);
dm_gpio_set_value(&priv->sck, 0);
dm_gpio_set_value(&priv->sstbz, 1);
}
static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
u32 addr, val;
int ret;
cpld_init();
ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
DM_GET_DRIVER(sysreset_renesas_ulcb),
&dev);
if (ret)
return ret;
if (argc == 2 && strcmp(argv[1], "info") == 0) {
printf("CPLD version:\t\t\t0x%08x\n",
cpld_read(CPLD_ADDR_VERSION));
cpld_read(dev, CPLD_ADDR_VERSION));
printf("H3 Mode setting (MD0..28):\t0x%08x\n",
cpld_read(CPLD_ADDR_MODE));
cpld_read(dev, CPLD_ADDR_MODE));
printf("Multiplexer settings:\t\t0x%08x\n",
cpld_read(CPLD_ADDR_MUX));
cpld_read(dev, CPLD_ADDR_MUX));
printf("DIPSW (SW6):\t\t\t0x%08x\n",
cpld_read(CPLD_ADDR_DIPSW6));
cpld_read(dev, CPLD_ADDR_DIPSW6));
return 0;
}
......@@ -143,10 +119,10 @@ static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
printf("0x%x\n", cpld_read(addr));
printf("0x%x\n", cpld_read(dev, addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
cpld_write(addr, val);
cpld_write(dev, addr, val);
}
return 0;
......@@ -160,8 +136,56 @@ U_BOOT_CMD(
"cpld write addr val\n"
);
void reset_cpu(ulong addr)
static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
cpld_write(dev, CPLD_ADDR_RESET, 1);
return -EINPROGRESS;
}
static int renesas_ulcb_sysreset_probe(struct udevice *dev)
{
cpld_init();
cpld_write(CPLD_ADDR_RESET, 1);
struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
GPIOD_IS_IN))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
GPIOD_IS_OUT))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
GPIOD_IS_OUT))
return -EINVAL;
/* PULL-UP on MISO line */
setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
/* Dummy read */
cpld_read(dev, CPLD_ADDR_VERSION);
return 0;
}
static struct sysreset_ops renesas_ulcb_sysreset = {
.request = renesas_ulcb_sysreset_request,
};
static const struct udevice_id renesas_ulcb_sysreset_ids[] = {
{ .compatible = "renesas,ulcb-cpld" },
{ }
};
U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
.name = "renesas_ulcb_sysreset",
.id = UCLASS_SYSRESET,
.ops = &renesas_ulcb_sysreset,
.probe = renesas_ulcb_sysreset_probe,
.of_match = renesas_ulcb_sysreset_ids,
.priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv),
};
......@@ -97,39 +97,15 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->ram_size += PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
fdtdec_setup_memory_banksize();
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RCAR_BOARD_STRING
};
......@@ -82,7 +82,7 @@ static struct hws_topology_map board_topology_map = {
BUS_WIDTH_16, /* memory_width */
MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */
0, 0, /* cas_wl cas_l */
HWS_TEMP_LOW, /* temperature */
HWS_TIM_DEFAULT} }, /* timing */
5, /* Num Of Bus Per Interface*/
......
......@@ -6,6 +6,7 @@ CONFIG_INTERNAL_UART=y
CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_VGA_BIOS_ADDR=0xfffb0000
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
......
......@@ -13,8 +13,8 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
......@@ -26,10 +26,14 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
......@@ -45,6 +49,7 @@ CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
......
......@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
......@@ -25,12 +26,18 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
......@@ -40,8 +47,10 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
......
......@@ -14,8 +14,8 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
......@@ -27,10 +27,14 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
......@@ -46,6 +50,7 @@ CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
......
......@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y