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  1. 06 Dec, 2017 1 commit
    • York Sun's avatar
      powerpc: mpc85xx: Fix static TLB table for SDRAM · 316f0d0f
      York Sun authored
      Most predefined TLB tables don't have memory coherence bit set for
      SDRAM. This wasn't an issue before invalidate_dcache_range() function
      was enabled. Without the coherence bit, dcache invalidation doesn't
      automatically flush the cache. The coherence bit is already set when
      dynamic TLB table is used. For some boards with different SPL boot
      method, or with legacy fixed setting, this bit needs to be set in
      TLB files.
      Signed-off-by: default avatarYork Sun <york.sun@nxp.com>
      316f0d0f
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  6. 17 Jan, 2008 3 commits