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  1. 06 Dec, 2017 1 commit
    • York Sun's avatar
      powerpc: mpc85xx: Fix static TLB table for SDRAM · 316f0d0f
      York Sun authored
      Most predefined TLB tables don't have memory coherence bit set for
      SDRAM. This wasn't an issue before invalidate_dcache_range() function
      was enabled. Without the coherence bit, dcache invalidation doesn't
      automatically flush the cache. The coherence bit is already set when
      dynamic TLB table is used. For some boards with different SPL boot
      method, or with legacy fixed setting, this bit needs to be set in
      TLB files.
      Signed-off-by: default avatarYork Sun <[email protected]>
      316f0d0f
  2. 19 Jan, 2016 1 commit
  3. 16 Jul, 2013 1 commit
  4. 02 May, 2013 1 commit
  5. 08 Aug, 2012 1 commit
  6. 16 Jul, 2010 1 commit
  7. 05 Jan, 2010 1 commit
  8. 12 Jun, 2009 1 commit
  9. 23 Jan, 2009 4 commits
  10. 13 Jan, 2009 1 commit
    • Haiying Wang's avatar
      Some changes of TLB entry setting for MPC8572DS · b5f65dfa
      Haiying Wang authored
      - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
      all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
      can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
      
      - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
      Signed-off-by: default avatarHaiying Wang <[email protected]>
      b5f65dfa
  11. 29 Oct, 2008 1 commit
  12. 18 Oct, 2008 2 commits
  13. 27 Aug, 2008 1 commit
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  15. 17 Jan, 2008 2 commits