Commit d865fd09 authored by Ricardo Ribalda Delgado's avatar Ricardo Ribalda Delgado Committed by Stefan Roese

ppc4xx: CPU PPC440x5 on Virtex5 FX

-This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by  Stefan Roese
Signed-off-by: default avatarRicardo Ribalda Delgado <[email protected]>
Acked-by: default avatarStefan Roese <[email protected]>
parent 42246dac
......@@ -35,10 +35,8 @@ SOBJS += kgdb.o
COBJS := 40x_spd_sdram.o
COBJS += 44x_spd_ddr.o
COBJS += 44x_spd_ddr2.o
COBJS += 4xx_enet.o
COBJS += 4xx_pci.o
COBJS += 4xx_pcie.o
COBJS += 4xx_uart.o
COBJS += bedbug_405.o
COBJS += commproc.o
COBJS += cpu.o
......@@ -47,11 +45,9 @@ COBJS += denali_data_eye.o
COBJS += denali_spd_ddr2.o
COBJS += ecc.o
COBJS += fdt.o
COBJS += gpio.o
COBJS += i2c.o
COBJS += interrupts.o
COBJS += iop480_uart.o
COBJS += miiphy.o
COBJS += ndfc.o
COBJS += sdram.o
COBJS += speed.o
......@@ -60,6 +56,15 @@ COBJS += traps.o
COBJS += usb.o
COBJS += usb_ohci.o
COBJS += usbdev.o
ifndef CONFIG_XILINX_440
COBJS += 4xx_enet.o
COBJS += 4xx_uart.o
COBJS += gpio.o
COBJS += miiphy.o
COBJS += uic.o
else
COBJS += xilinx_irq.o
endif
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
......
......@@ -279,7 +279,11 @@ int checkcpu (void)
get_sys_info(&sys_info);
#if defined(CONFIG_XILINX_440)
puts("IBM PowerPC 4");
#else
puts("AMCC PowerPC 4");
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
......@@ -542,6 +546,10 @@ int checkcpu (void)
strcpy(addstr, "No Security support");
break;
case PVR_VIRTEX5:
puts("x5 VIRTEX5");
break;
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;
......
......@@ -8,6 +8,10 @@
* (C) Copyright 2003 (440GX port)
* Travis B. Sawyer, Sandburst Corporation, [email protected]
*
* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
* Ricardo Ribalda-Universidad Autonoma de [email protected]
* Work supported by Qtechnology (htpp://qtec.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -31,23 +35,11 @@
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/interrupt.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
#if (UIC_MAX > 3)
#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
#elif (UIC_MAX > 2)
#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
#elif (UIC_MAX > 1)
#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
#else
#define UICB0_ALL 0
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
......@@ -58,11 +50,7 @@ struct irq_action {
void *arg;
int count;
};
static struct irq_action irq_vecs[UIC_MAX * 32];
u32 get_dcr(u16);
void set_dcr(u16, u32);
static struct irq_action irq_vecs[IRQ_MAX];
#if defined(CONFIG_440)
......@@ -103,7 +91,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
/*
* Mark all irqs as free
*/
for (vec = 0; vec < (UIC_MAX * 32); vec++) {
for (vec = 0; vec < IRQ_MAX; vec++) {
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
irq_vecs[vec].count = 0;
......@@ -147,110 +135,36 @@ int interrupt_init_cpu (unsigned *decrementer_count)
*/
set_evpr(0x00000000);
#if (UIC_MAX > 1)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
#endif
#if (UIC_MAX > 2)
irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
#endif
#if (UIC_MAX > 3)
irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
#endif
/*
*Call uic or xilinx_irq pic_enable
*/
pic_enable();
return (0);
}
/* Handler for UIC interrupt */
static void uic_interrupt(u32 uic_base, int vec_base)
void timer_interrupt_cpu(struct pt_regs *regs)
{
u32 uic_msr;
u32 msr_shift;
int vec;
/*
* Read masked interrupt status register to determine interrupt source
*/
uic_msr = get_dcr(uic_base + UIC_MSR);
msr_shift = uic_msr;
vec = vec_base;
while (msr_shift != 0) {
if (msr_shift & 0x80000000) {
/*
* Increment irq counter (for debug purpose only)
*/
irq_vecs[vec].count++;
if (irq_vecs[vec].handler != NULL) {
/* call isr */
(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
} else {
set_dcr(uic_base + UIC_ER,
get_dcr(uic_base + UIC_ER) & ~UIC_MASK(vec));
printf("Masking bogus interrupt vector %d"
" (UIC_BASE=0x%x)\n", vec, uic_base);
}
/*
* After servicing the interrupt, we have to remove the
* status indicator
*/
set_dcr(uic_base + UIC_SR, UIC_MASK(vec));
}
/*
* Shift msr to next position and increment vector
*/
msr_shift <<= 1;
vec++;
}
/* nothing to do here */
return;
}
/*
* Handle external interrupts
*/
void external_interrupt(struct pt_regs *regs)
void interrupt_run_handler(int vec)
{
u32 uic_msr;
/*
* Read masked interrupt status register to determine interrupt source
*/
uic_msr = mfdcr(uic0msr);
#if (UIC_MAX > 1)
if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
uic_interrupt(UIC1_DCR_BASE, 32);
#endif
#if (UIC_MAX > 2)
if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
uic_interrupt(UIC2_DCR_BASE, 64);
#endif
#if (UIC_MAX > 3)
if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
uic_interrupt(UIC3_DCR_BASE, 96);
#endif
if (uic_msr & ~(UICB0_ALL))
uic_interrupt(UIC0_DCR_BASE, 0);
mtdcr(uic0sr, uic_msr);
irq_vecs[vec].count++;
if (irq_vecs[vec].handler != NULL) {
/* call isr */
(*irq_vecs[vec].handler) (irq_vecs[vec].arg);
} else {
pic_irq_disable(vec);
printf("Masking bogus interrupt vector %d\n", vec);
}
pic_irq_ack(vec);
return;
}
/*
* Install and free a interrupt handler.
*/
void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
{
/*
......@@ -263,51 +177,19 @@ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
irq_vecs[vec].handler = handler;
irq_vecs[vec].arg = arg;
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
#endif
#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
#endif
#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
#endif
debug("Install interrupt for vector %d ==> %p\n", vec, handler);
pic_irq_enable(vec);
return;
}
void irq_free_handler (int vec)
void irq_free_handler(int vec)
{
debug("Free interrupt for vector %d ==> %p\n",
vec, irq_vecs[vec].handler);
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
#endif
#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
#endif
#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
#endif
pic_irq_disable(vec);
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
}
void timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
}
......@@ -319,7 +201,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("Interrupt-Information:\n");
printf ("Nr Routine Arg Count\n");
for (vec = 0; vec < (UIC_MAX * 32); vec++) {
for (vec = 0; vec < IRQ_MAX; vec++) {
if (irq_vecs[vec].handler != NULL) {
printf ("%02d %08lx %08lx %d\n",
vec,
......
......@@ -416,7 +416,8 @@ ulong get_PCI_freq (void)
return sys_info.freqPCI;
}
#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) \
&& !defined(CONFIG_XILINX_440)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
......@@ -449,6 +450,8 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqUART = sysInfo->freqPLB;
}
#else
#if !defined(CONFIG_XILINX_440)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
......@@ -535,6 +538,7 @@ void get_sys_info (sys_info_t * sysInfo)
}
#endif
#endif /* CONFIG_XILINX_440 */
#if defined(CONFIG_YUCCA)
unsigned long determine_sysper(void)
......
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, [email protected]
*
* (C) Copyright 2002 (440 port)
* Scott McNutt, Artesyn Communication Producs, [email protected]
*
* (C) Copyright 2003 (440GX port)
* Travis B. Sawyer, Sandburst Corporation, [email protected]
*
* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
* Ricardo Ribalda-Universidad Autonoma de [email protected]
* Work supported by Qtechnology (htpp://qtec.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/interrupt.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
#if (UIC_MAX > 3)
#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
#elif (UIC_MAX > 2)
#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
#elif (UIC_MAX > 1)
#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
#else
#define UICB0_ALL 0
#endif
u32 get_dcr(u16);
DECLARE_GLOBAL_DATA_PTR;
void pic_enable(void)
{
#if (UIC_MAX > 1)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt,
0);
#endif
#if (UIC_MAX > 2)
irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt,
0);
#endif
#if (UIC_MAX > 3)
irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt,
0);
irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt,
0);
#endif
}
/* Handler for UIC interrupt */
static void uic_interrupt(u32 uic_base, int vec_base)
{
u32 uic_msr;
u32 msr_shift;
int vec;
/*
* Read masked interrupt status register to determine interrupt source
*/
uic_msr = get_dcr(uic_base + UIC_MSR);
msr_shift = uic_msr;
vec = vec_base;
while (msr_shift != 0) {
if (msr_shift & 0x80000000)
interrupt_run_handler(vec);
/*
* Shift msr to next position and increment vector
*/
msr_shift <<= 1;
vec++;
}
}
/*
* Handle external interrupts
*/
void external_interrupt(struct pt_regs *regs)
{
u32 uic_msr;
/*
* Read masked interrupt status register to determine interrupt source
*/
uic_msr = mfdcr(uic0msr);
#if (UIC_MAX > 1)
if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
uic_interrupt(UIC1_DCR_BASE, 32);
#endif
#if (UIC_MAX > 2)
if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
uic_interrupt(UIC2_DCR_BASE, 64);
#endif
#if (UIC_MAX > 3)
if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
uic_interrupt(UIC3_DCR_BASE, 96);
#endif
if (uic_msr & ~(UICB0_ALL))
uic_interrupt(UIC0_DCR_BASE, 0);
mtdcr(uic0sr, uic_msr);
return;
}
void pic_irq_ack(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicsr, UIC_MASK(vec));
#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1sr, UIC_MASK(vec));
#endif
#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2sr, UIC_MASK(vec));
#endif
#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3sr, UIC_MASK(vec));
#endif
}
/*
* Install and free a interrupt handler.
*/
void pic_irq_enable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
#endif
#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
#endif
#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
#endif
debug("Install interrupt for vector %d ==> %p\n", vec, handler);
}
void pic_irq_disable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
#if (UIC_MAX > 1)
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
#endif
#if (UIC_MAX > 2)
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
#endif
#if (UIC_MAX > 3)
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
#endif
}
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de [email protected]
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software [email protected]
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/interrupt.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
#include <asm/io.h>
#include <asm/xilinx_irq.h>
DECLARE_GLOBAL_DATA_PTR;
void pic_enable(void)
{
debug("Xilinx PIC at 0x%8x\n", intc);
/*
* Disable all external interrupts until they are
* explicitly requested.
*/
out_be32((u32 *) IER, 0);
/* Acknowledge any pending interrupts just in case. */
out_be32((u32 *) IAR, 0xffffffff);
/* Turn on the Master Enable. */
out_be32((u32 *) MER, 0x3UL);
return;
}
int xilinx_pic_irq_get(void)
{
u32 irq;
irq = in_be32((u32 *) IVR);
/* If no interrupt is pending then all bits of the IVR are set to 1. As
* the IVR is as many bits wide as numbers of inputs are available.
* Therefore, if all bits of the IVR are set to one, its content will
* be bigger than XPAR_INTC_MAX_NUM_INTR_INPUTS.
*/
if (irq >= XPAR_INTC_MAX_NUM_INTR_INPUTS)
irq = -1; /* report no pending interrupt. */
debug("get_irq: %d\n", irq);
return (irq);
}
void pic_irq_enable(unsigned int irq)
{
u32 mask = IRQ_MASK(irq);
debug("enable: %d\n", irq);
out_be32((u32 *) SIE, mask);
}
void pic_irq_disable(unsigned int irq)
{
u32 mask = IRQ_MASK(irq);
debug("disable: %d\n", irq);
out_be32((u32 *) CIE, mask);
}
void pic_irq_ack(unsigned int irq)
{
u32 mask = IRQ_MASK(irq);
debug("ack: %d\n", irq);
out_be32((u32 *) IAR, mask);
}
void external_interrupt(struct pt_regs *regs)
{
int irq;
irq = xilinx_pic_irq_get();
if (irq < 0)
return;
interrupt_run_handler(irq);
return;
}
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de [email protected]
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef INTERRUPT_H
#define INTERRUPT_H
#if defined(CONFIG_XILINX_440)
#include <asm/xilinx_irq.h>
#else
#include <asm/ppc4xx-uic.h>
#endif
void pic_enable(void);
void pic_irq_enable(unsigned int irq);
void pic_irq_disable(unsigned int irq);
void pic_irq_ack(unsigned int irq);
void external_interrupt(struct pt_regs *regs);
void interrupt_run_handler(int vec);
#endif
......@@ -43,6 +43,8 @@
#define UIC_MAX 1
#endif