Commit 6f1ee8a4 authored by Tom Rini's avatar Tom Rini
parents 335f7b12 e80dac0a
......@@ -65,6 +65,14 @@ S: Maintained
L: [email protected]
F: drivers/gpio/hsdk-creg-gpio.c
ARC HSDK CGU CLOCK
M: Eugeniy Paltsev <[email protected]>
S: Maintained
L: [email protected]
F: drivers/clk/clk-hsdk-cgu.c
F: include/dt-bindings/clock/snps,hsdk-cgu.h
F: doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
ARM
M: Albert Aribaud <[email protected]>
S: Maintained
......
......@@ -27,6 +27,12 @@
#define ARC_AUX_IC_PTAG 0x1E
#endif
#define ARC_BCR_IC_BUILD 0x77
#define AUX_AUX_CACHE_LIMIT 0x5D
#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
/* ICCM and DCCM auxiliary registers */
#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
......@@ -72,6 +78,9 @@
/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val) \
__builtin_arc_sr((unsigned int)val, reg_immed)
/* ARCNUM [15:8] - field to identify each core in a multi-core system */
#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARC_ARCREGS_H */
#include <asm-generic/gpio.h>
......@@ -32,15 +32,15 @@
* relocation but will be used after being zeroed.
*/
int l1_line_sz __section(".data");
int dcache_exists __section(".data");
int icache_exists __section(".data");
bool dcache_exists __section(".data") = false;
bool icache_exists __section(".data") = false;
#define CACHE_LINE_MASK (~(l1_line_sz - 1))
#ifdef CONFIG_ISA_ARCV2
int slc_line_sz __section(".data");
int slc_exists __section(".data");
int ioc_exists __section(".data");
bool slc_exists __section(".data") = false;
bool ioc_exists __section(".data") = false;
static unsigned int __before_slc_op(const int op)
{
......@@ -152,7 +152,7 @@ static void read_decode_cache_bcr_arcv2(void)
sbcr.word = read_aux_reg(ARC_BCR_SLC);
if (sbcr.fields.ver) {
slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
slc_exists = 1;
slc_exists = true;
slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
}
......@@ -169,7 +169,7 @@ static void read_decode_cache_bcr_arcv2(void)
cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
if (cbcr.fields.c)
ioc_exists = 1;
ioc_exists = true;
}
#endif
......@@ -190,7 +190,7 @@ void read_decode_cache_bcr(void)
ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
if (ibcr.fields.ver) {
icache_exists = 1;
icache_exists = true;
l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
if (!ic_line_sz)
panic("Instruction exists but line length is 0\n");
......@@ -198,7 +198,7 @@ void read_decode_cache_bcr(void)
dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
if (dbcr.fields.ver){
dcache_exists = 1;
dcache_exists = true;
l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
if (!dc_line_sz)
panic("Data cache exists but line length is 0\n");
......
......@@ -26,6 +26,10 @@ int board_early_init_f(void)
return 0;
}
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
int board_mmc_init(bd_t *bis)
{
struct dwmci_host *host = NULL;
......@@ -36,12 +40,18 @@ int board_mmc_init(bd_t *bis)
return 1;
}
/*
* Switch SDIO external ciu clock divider from default div-by-8 to
* minimum possible div-by-2.
*/
writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
memset(host, 0, sizeof(struct dwmci_host));
host->name = "Synopsys Mobile storage";
host->ioaddr = (void *)ARC_DWMMC_BASE;
host->buswidth = 4;
host->dev_index = 0;
host->bus_hz = 100000000;
host->bus_hz = 50000000;
add_dwmci(host, host->bus_hz / 2, 400000);
......
* Synopsys HSDK clock generation unit
The Synopsys HSDK clock controller generates and supplies clock to various
controllers and peripherals within the SoC.
Required Properties:
- compatible: should be "snps,hsdk-cgu-clock"
- reg: the pair of physical base address and length of clock generation unit
memory mapped region and creg arc core divider memory mapped region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
used in device tree sources.
Example: Clock controller node:
cgu_clk: [email protected] {
compatible = "snps,hsdk-cgu-clock";
reg = <0xf0000000 0x1000>, <0xf00014B8 0x4>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart0: [email protected] {
compatible = "snps,dw-apb-uart";
reg = <0xf0005000 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cgu_clk CLK_SYS_UART_REF>;
};
......@@ -54,6 +54,12 @@ config CLK_STM32F
This clock driver adds support for RCC clock management
for STM32F4 and STM32F7 SoCs.
config CLK_HSDK
bool "Enable cgu clock driver for HSDK"
depends on CLK
help
Enable this to support the cgu clocks on Synopsys ARC HSDK
config CLK_ZYNQ
bool "Enable clock driver support for Zynq"
depends on CLK && ARCH_ZYNQ
......
......@@ -20,6 +20,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
This diff is collapsed.
/*
* Synopsys HSDK SDP CGU clock driver dts bindings
*
* Copyright (C) 2017 Synopsys
* Author: Eugeniy Paltsev <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_
#define __DT_BINDINGS_CLK_HSDK_CGU_H_
#define CLK_ARC_PLL 0
#define CLK_ARC 1
#define CLK_DDR_PLL 2
#define CLK_SYS_PLL 3
#define CLK_SYS_APB 4
#define CLK_SYS_AXI 5
#define CLK_SYS_ETH 6
#define CLK_SYS_USB 7
#define CLK_SYS_SDIO 8
#define CLK_SYS_HDMI 9
#define CLK_SYS_GFX_CORE 10
#define CLK_SYS_GFX_DMA 11
#define CLK_SYS_GFX_CFG 12
#define CLK_SYS_DMAC_CORE 13
#define CLK_SYS_DMAC_CFG 14
#define CLK_SYS_SDIO_REF 15
#define CLK_SYS_SPI_REF 16
#define CLK_SYS_I2C_REF 17
#define CLK_SYS_UART_REF 18
#define CLK_SYS_EBI_REF 19
#define CLK_TUN_PLL 20
#define CLK_TUN 21
#define CLK_HDMI_PLL 22
#define CLK_HDMI 23
#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
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