Commit 01a00431 authored by Ricardo Ribalda Delgado's avatar Ricardo Ribalda Delgado Committed by Stefan Roese

ppc4xx: ML507: U-Boot in flash and System ACE

This patch allows booting from FLASH the ML507 board by Xilinx.
Previously, U-Boot needed to be loaded from JTAG or a Sytem ACE CF
Signed-off-by: default avatarRicardo Ribalda Delgado <[email protected]>
Signed-off-by: default avatarStefan Roese <[email protected]>
parent 60204d06
......@@ -210,6 +210,7 @@ LIST_4xx=" \
ML2 \
ml300 \
ml507 \
ml507_flash \
ocotea \
OCRTC \
ORSG \
......
......@@ -1349,7 +1349,15 @@ ML2_config: unconfig
ml300_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
ml507_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@cp $(obj)board/xilinx/ml507/u-boot-rom.lds $(obj)board/xilinx/ml507/u-boot.lds
@echo "TEXT_BASE = 0xFE3E0000" > $(obj)board/xilinx/ml507/config.tmp
@$(MKCONFIG) $(@:_flash_config=) ppc ppc4xx ml507 xilinx
ml507_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
@cp $(obj)board/xilinx/ml507/u-boot-ram.lds $(obj)board/xilinx/ml507/u-boot.lds
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx
ocotea_config: unconfig
......
......@@ -20,5 +20,8 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0x04000000
endif
......@@ -35,13 +35,19 @@ tlbentry(XPAR_UARTLITE_0_BASEADDR, SZ_64K, XPAR_UARTLITE_0_BASEADDR, 0,
/* PIC */
tlbentry(XPAR_INTC_0_BASEADDR, SZ_64K, XPAR_INTC_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#ifdef XPAR_IIC_EEPROM_BASEADDR
/* I2C */
tlbentry(XPAR_IIC_EEPROM_BASEADDR, SZ_64K, XPAR_IIC_EEPROM_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#endif
#ifdef XPAR_LLTEMAC_0_BASEADDR
/* Net */
tlbentry(XPAR_LLTEMAC_0_BASEADDR, SZ_64K, XPAR_LLTEMAC_0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
#endif
#ifdef XPAR_FLASH_MEM0_BASEADDR
/*Flash*/
tlbentry(XPAR_FLASH_MEM0_BASEADDR, SZ_256M, XPAR_FLASH_MEM0_BASEADDR, 0,
AC_R | AC_W | SA_G | SA_I)
AC_R | AC_W | AC_X | SA_G | SA_I)
#endif
tlbtab_end
/*
* (C) Copyright 2000
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, [email protected]
* 2008:
* Modified by: Ricardo Ribalda Delgado [email protected]
*
* See file CREDITS for list of people who contributed to this
* project.
......@@ -25,8 +23,7 @@
OUTPUT_ARCH(powerpc)
ENTRY(_start_440)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
......@@ -55,6 +52,10 @@ SECTIONS
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
*(.text)
*(.fixup)
*(.got1)
......@@ -125,6 +126,9 @@ SECTIONS
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, [email protected]
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
ENTRY(_start_440)
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}
......@@ -22,13 +22,14 @@
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_LLTEMAC_0_BASEADDR 0x81c00000
#define XPAR_FLASH_MEM0_BASEADDR 0xFC000000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif
......@@ -31,15 +31,14 @@
/*Mem Map*/
#define CFG_SDRAM_BASE 0x0
#define CFG_SDRAM_SIZE_MB 256
#define CFG_MONITOR_BASE 0x04000000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN ( 192 * 1024 )
#define CFG_MALLOC_LEN ( 128 * 1024 )
#define CFG_ISRAM_BASE XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR
/*Uart*/
#define CONFIG_XILINX_UARTLITE
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE {9600}
#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE }
#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
/*Cmd*/
......@@ -75,9 +74,9 @@
#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 )
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x400000 /* default load address */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
......@@ -101,7 +100,7 @@
#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE )
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*Speed*/
#define CONFIG_SYS_CLK_FREQ 400000000
#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ
/*Flash*/
#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
......@@ -110,7 +109,7 @@
#define CFG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_EMPTY_INFO 1
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT ( CFG_FLASH_SIZE / ( 64 * 1024 ) )
#define CFG_MAX_FLASH_SECT 259
#define CFG_FLASH_PROTECTION
#endif /* __CONFIG_H */
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