Vivado block designs are not usable for simulation with tsfpga
Hi, I have been testing out tsfpga for quite some time with very positive outcome. However I did hit a roadblock lately:
When creating Vivado Block Design, and exporting it through write_bd_tcl
the generated output is not usable with for simulation.
While build creates the needed hierarchy properly, the simulate path does not generate any products necessary to run simulation with.
This happens both when putting the generated tcl as IpCoreFile
or when adding it through tcl_sources
to VivadoProject.
Is this expected or is there any proper way to include the Block Designs properly in tsfpga flow for simulation?
Edited by Szymon