core now outputs all necessary constants so that block controller can generate...

core now outputs all necessary constants so that block controller can generate the correct coefficients modified: fpga-rfnoc/m2_channelizer/noc_block_channelizer.v modified: fpga-src/axi_m2_channelizer/src/verilog/axi_fifo_18.v modified: fpga-src/axi_m2_channelizer/src/verilog/axi_fifo_19.v modified: fpga-src/axi_m2_channelizer/src/verilog/axi_fifo_2.v modified: fpga-src/axi_m2_channelizer/src/verilog/axi_fifo_3.v modified: fpga-src/axi_m2_channelizer/src/verilog/axi_fifo_51.v modified: fpga-src/axi_m2_channelizer/src/verilog/axi_fifo_64.v modified: fpga-src/axi_m2_channelizer/src/verilog/chan_top_2x_2048M_16iw_16ow_32tps.v modified: fpga-src/axi_m2_channelizer/src/verilog/chan_top_2x_2048M_16iw_16ow_32tps_sim.do modified: fpga-src/axi_m2_channelizer/src/verilog/chan_top_2x_2048M_16iw_16ow_32tps_tb.v modified: fpga-src/axi_m2_channelizer/src/verilog/cic_M256_N1_R1_iw5_0.v modified: fpga-src/axi_m2_channelizer/src/verilog/cic_M256_N1_R1_iw5_0_correction_sp_rom.v modified: fpga-src/axi_m2_channelizer/src/verilog/cic_M256_N1_R1_iw5_0_offset_sp_rom.v modified: fpga-src/axi_m2_channelizer/src/verilog/circ_buffer.v modified: fpga-src/axi_m2_channelizer/src/verilog/comb_M256_N1_iw5_0.v modified: fpga-src/axi_m2_channelizer/src/verilog/count_cycle_cw16_18.v modified: fpga-src/axi_m2_channelizer/src/verilog/count_cycle_cw16_65.v modified: fpga-src/axi_m2_channelizer/src/verilog/count_cycle_cw16_8.v modified: fpga-src/axi_m2_channelizer/src/verilog/downselect_2048.v modified: fpga-src/axi_m2_channelizer/src/verilog/dp_block_read_first_ram.v modified: fpga-src/axi_m2_channelizer/src/verilog/dp_block_write_first_ram.v modified: fpga-src/axi_m2_channelizer/src/verilog/dsp48_cic_M256_N1_R1_iw5_0.v modified: fpga-src/axi_m2_channelizer/src/verilog/dsp48_cic_M256_N1_R1_iw5_0_corr.v modified: fpga-src/axi_m2_channelizer/src/verilog/dsp48_comb_M256_N1_iw5_0.v modified: fpga-src/axi_m2_channelizer/src/verilog/dsp48_pfb_mac.v modified: fpga-src/axi_m2_channelizer/src/verilog/dsp48_pfb_mac_0.v modified: fpga-src/axi_m2_channelizer/src/verilog/dsp48_pfb_rnd.v modified: fpga-src/axi_m2_channelizer/src/verilog/exp_shifter_2048Mmax_16iw_256avg_len.v modified: fpga-src/axi_m2_channelizer/src/verilog/grc_word_reader.sv modified: fpga-src/axi_m2_channelizer/src/verilog/grc_word_writer.sv modified: fpga-src/axi_m2_channelizer/src/verilog/input_buffer.v modified: fpga-src/axi_m2_channelizer/src/verilog/mem_ctrl_pfb_2x_2048Mmax_16iw_16ow_32tps.v modified: fpga-src/axi_m2_channelizer/src/verilog/pfb_2x_2048Mmax_16iw_16ow_32tps.v modified: fpga-src/axi_m2_channelizer/src/verilog/pfb_2x_2048Mmax_16iw_16ow_32tps_dp_rom.v modified: fpga-src/axi_m2_channelizer/src/verilog/pipe_mux_2048_1.v modified: fpga-src/axi_m2_channelizer/src/verilog/slicer_48_13.v