Commit 6dede87f authored by Alexander Shabarshin's avatar Alexander Shabarshin

next iteration

parent ec7deab8
......@@ -28,23 +28,31 @@ class OPC1 : public Entity
const Wire<5> RTS, LXA; // SEE BELOW
// reg [10:0] OR_q, PC_q;
Wire<11> OR_q;
Uint<11> PC_q;
Wire<11> OR_q,OR_q_REG;
Uint<11> PC_q,PC_q_REG;
// reg [7:0] ACC_q;
Uint<8> ACC_q;
Uint<8> ACC_q,ACC_q_REG;
// reg [2:0] FSM_q;
Uint<3> FSM_q;
Uint<3> FSM_q,FSM_q_REG;
// reg [4:0] IR_q;
Wire<5> IR_q;
Wire<5> IR_q,IR_q_REG;
// reg [2:0] LINK_q; // bottom bit doubles up as carry flag
Wire<3> LINK_q;
Wire<3> LINK_q,LINK_q_REG;
// SHOUD WE HAVE A MACROS REG(Wire<3>,LINK_q)?
//`define CARRY LINK_q[0]
#define CARRY LINK_q[0]
// BUT FOR THE LEFT SIDE WE NEED TO USE TEMPORARY COPY!!!
#define CARRY_REG LINK_q_REG[0]
// TEMPORARY SIGNALS:
Signal reset_b, writeback_w, rnw;
Wire<11> address;
Wire<8> data; // it's all Z by default
// IMPLEMENTATION OF INTERFACE (inout[7:0] data, output[10:0] address, output rnw, input clk, input reset_b);
......@@ -68,16 +76,15 @@ class OPC1 : public Entity
void step()
{
Signal reset_b = io(i_reset_b).read();
reset_b = io(i_reset_b).read();
// wire writeback_w = ((FSM_q == EXEC) && (IR_q == STA || IR_q == STAP)) & reset_b ;
Signal writeback_w = ((FSM_q == EXEC) && (IR_q == STA || IR_q == STAP)) & reset_b ;
writeback_w = ((FSM_q == EXEC) && (IR_q == STA || IR_q == STAP)) & reset_b ;
// assign rnw = ~writeback_w ;
Signal rnw = ~writeback_w;
rnw = ~writeback_w;
// assign data = (writeback_w)?ACC_q:8'bz ;
Wire<8> data; // it's all Z by default
if(writeback_w) data = ACC_q;
else // below required for later logic
{
......@@ -85,43 +92,43 @@ class OPC1 : public Entity
}
// assign address = ( writeback_w || FSM_q == RDMEM || FSM_q==RDMEM2)? OR_q:PC_q;
Wire<11> address = ( (bool)writeback_w || FSM_q == RDMEM || FSM_q==RDMEM2 )? OR_q:PC_q;
address = ( (bool)writeback_w || FSM_q == RDMEM || FSM_q == RDMEM2 )? OR_q:PC_q;
// always @ (posedge clk or negedge reset_b )
if(posedge(i_clk) || negedge(i_reset_b))
if(posedge(i_clk) || negedge(i_reset_b)) // WRITE FSM_q
{
// if (!reset_b)
if (!reset_b)
// FSM_q <= FETCH0;
FSM_q = FETCH0;
FSM_q_REG = FETCH0;
// else
else
{
// case(FSM_q)
// FETCH0 : FSM_q <= FETCH1;
if(FSM_q == FETCH0) FSM_q = FETCH1;
if(FSM_q_REG == FETCH0) FSM_q = FETCH1;
// FETCH1 : FSM_q <= (IR_q[4])?EXEC:RDMEM ;
else if(FSM_q == FETCH1) FSM_q = (IR_q[4]==TRUE)?EXEC:RDMEM;
else if(FSM_q == FETCH1) FSM_q_REG = (IR_q[4]==TRUE)?EXEC:RDMEM;
// RDMEM : FSM_q <= (IR_q==LDAP)?RDMEM2:EXEC;
else if(FSM_q == RDMEM) FSM_q = (IR_q==LDAP)?RDMEM2:EXEC;
else if(FSM_q == RDMEM) FSM_q_REG = (IR_q==LDAP)?RDMEM2:EXEC;
// RDMEM2 : FSM_q <= EXEC;
else if(FSM_q == RDMEM2) FSM_q = EXEC;
else if(FSM_q == RDMEM2) FSM_q_REG = EXEC;
// EXEC : FSM_q <= FETCH0;
else if(FSM_q == EXEC) FSM_q = FETCH0;
else if(FSM_q == EXEC) FSM_q_REG = FETCH0;
// endcase
}
}
// always @ (posedge clk)
if(posedge(i_clk))
if(posedge(i_clk)) // WRITE IR_q, OR_q, LINK_q, ACC_q and CARRY
// begin
{
......@@ -129,11 +136,11 @@ class OPC1 : public Entity
// IR_q <= (FSM_q == FETCH0)? data[7:3] : IR_q;
if(FSM_q == FETCH0)
{
IR_q[0] = data[3];
IR_q[1] = data[4];
IR_q[2] = data[5];
IR_q[3] = data[6];
IR_q[4] = data[7];
IR_q_REG[0] = data[3];
IR_q_REG[1] = data[4];
IR_q_REG[2] = data[5];
IR_q_REG[3] = data[6];
IR_q_REG[4] = data[7];
}
// // OR_q[10:8] is upper part nybble for address - needs to be zeroed
......@@ -141,15 +148,15 @@ class OPC1 : public Entity
// OR_q[10:8] <= (FSM_q == FETCH0)? data[2:0]: (FSM_q==RDMEM)?3'b0:OR_q[10:8];
if(FSM_q == FETCH0)
{
OR_q[8] = data[0];
OR_q[9] = data[1];
OR_q[10] = data[2];
OR_q_REG[8] = data[0];
OR_q_REG[9] = data[1];
OR_q_REG[10] = data[2];
}
else if(FSM_q == RDMEM)
{
OR_q[8] = FALSE;
OR_q[9] = FALSE;
OR_q[10] = FALSE;
OR_q_REG[8] = FALSE;
OR_q_REG[9] = FALSE;
OR_q_REG[10] = FALSE;
}
// OR_q[7:0] <= data; //Lowest byte of OR is dont care in FETCH0 and at end of EXEC
......@@ -163,57 +170,62 @@ class OPC1 : public Entity
// JSR : {LINK_q,ACC_q} <= PC_q ;
if(IR_q==JSR)
{
LINK_q = PC_q.part(8,10);
ACC_q = PC_q.part(0,7);
LINK_q_REG = PC_q.part(8,10);
ACC_q_REG = PC_q.part(0,7);
}
// LXA : {LINK_q,ACC_q} <= {ACC_q[2:0], 5'b0, LINK_q};
else if(IR_q==LXA)
{
LINK_q = ACC_q.part(0,2);
LINK_q_REG = ACC_q.part(0,2);
for(int i=7;i>=0;i--)
{
if(i>=3) ACC_q[i] = FALSE;
else ACC_q[i] = LINK_q[i];
if(i>=3) ACC_q_REG[i] = FALSE;
else ACC_q_REG[i] = LINK_q[i];
}
}
// AND : {`CARRY, ACC_q} <= {1'b0, ACC_q & OR_q[7:0]};
else if(IR_q==AND)
{
CARRY = FALSE;
ACC_q = ACC_q & OR_q.part(0,7);
CARRY_REG = FALSE;
ACC_q_REG = ACC_q & OR_q.part(0,7);
}
// NOT : ACC_q <= ~OR_q[7:0];
else if(IR_q==NOT)
{
ACC_q = ~OR_q.part(0,7);
ACC_q_REG = ~OR_q.part(0,7);
}
// LDA : ACC_q <= OR_q[7:0];
else if(IR_q==LDA)
{
ACC_q = OR_q.part(0,7);
ACC_q_REG = OR_q.part(0,7);
}
// LDAP : ACC_q <= OR_q[7:0];
else if(IR_q==LDAP)
{
ACC_q = OR_q.part(0,7);
ACC_q_REG = OR_q.part(0,7);
}
// ADD : {`CARRY,ACC_q} <= ACC_q + `CARRY + OR_q[7:0];
else if(IR_q==ADD)
{
ACC_q += OR_q.part(0,7);
if(CARRY==TRUE) ACC_q++;
ACC_q_REG = ACC_q + (CARRY==TRUE)?1:0 + OR_q.part(0,7);
if(ACC_q.overflow())
CARRY = TRUE;
else CARRY = FALSE;
CARRY_REG = TRUE;
else CARRY_REG = FALSE;
}
// default: {`CARRY,ACC_q} <= {`CARRY,ACC_q};
else
{
CARRY_REG = CARRY;
ACC_q_REG = ACC_q;
}
// endcase
}
......@@ -221,14 +233,14 @@ class OPC1 : public Entity
}
// always @ (posedge clk or negedge reset_b )
if(posedge(i_clk) || negedge(i_reset_b))
if(posedge(i_clk) || negedge(i_reset_b)) // WRITE PC_q
{
// if (!reset_b) // On reset start execution at 0x100 to leave page zero clear for variables
if(!reset_b)
// PC_q <= 11'h100;
PC_q = 0x100;
PC_q_REG = 0x100;
// else
else
......@@ -237,7 +249,7 @@ class OPC1 : public Entity
if(FSM_q==FETCH0 || FSM_q==FETCH1)
// PC_q <= PC_q + 1;
PC_q++;
PC_q_REG = PC_q + 1;
// else
else
......@@ -247,25 +259,25 @@ class OPC1 : public Entity
// JP : PC_q <= OR_q;
if(IR_q==JP)
{
PC_q = OR_q;
PC_q_REG = OR_q;
}
// JPC : PC_q <= (`CARRY)?OR_q:PC_q;
else if(IR_q==JPC)
{
PC_q = (CARRY==TRUE)?OR_q:PC_q;
PC_q_REG = (CARRY==TRUE)?OR_q:PC_q;
}
// JPZ : PC_q <= ~(|ACC_q)?OR_q:PC_q;
else if(IR_q==JPZ)
{
PC_q = (ACC_q==0)?OR_q:PC_q;
PC_q_REG = ((unsigned)ACC_q==0)?OR_q:PC_q;
}
// JSR : PC_q <= OR_q;
else if(IR_q==JSR)
{
PC_q = OR_q;
PC_q_REG = OR_q;
}
// RTS : PC_q <= {LINK_q, ACC_q};
......@@ -273,15 +285,24 @@ class OPC1 : public Entity
{
for(int i=10;i>=0;i--)
{
if(i>=8) PC_q[i]=LINK_q[i-8];
else PC_q[i]=ACC_q[i];
if(i>=8) PC_q_REG[i]=LINK_q[i-8];
else PC_q_REG[i]=ACC_q[i];
}
}
// default: PC_q <= PC_q;
else PC_q_REG = PC_q;
// endcase
}
OR_q = OR_q_REG;
PC_q = PC_q_REG;
ACC_q = ACC_q_REG;
FSM_q = FSM_q_REG;
IR_q = IR_q_REG;
LINK_q = LINK_q_REG;
if(writeback_w)
{
for(int i=0;i<8;i++) io(i_data) << data[i];
......
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