Loop & Branch nesting is broken for the SPIR-V backend
Nesting loops and branches too much is currently broken. The reason being, that the emitted pattern works for simple loops, but breaks for anything more involved. However, for it to be fixed we need a the CFG recovery described in the RVSDG source material.
I'll implement it in terms of a RVSDG<N,E> -> CSG<N,E>
pass. So the simpl-nodes and edges stay the same, but are expressed in the CFG instead of the RVSDG.