Modules/Clock-Divider-(clockDiv16).md

+* Used to generate SPI clock from system clock.
+* Outputs a clock array with 16 diffrent frequencies.
+
+| Post | Orientation | Width |  Description |
+| :------: | :------: | :------: | ------ |
+| `clk_i`  | Input | 1 | System Clock |
+| `rst`  | Input | 1 | System Reset |
+| `clk_o`  | Output | 16 | Generated clock array |
+
+Generated clock frequencies (`clk_o[n]`) for 100 MHz `clk_i` can be found below.
+
+| Address (n) | Output Frequency | [f] |
+| :------: | :------: | :------: |
+| 0000 |   50  | MHz |
+|  0001 |   25    |   MHz |
+| 0010  |  12.5    | MHz  |
+|  0011  |   6.25  |  MHz |
+|  0100  |   3.125 |  MHz |
+|  0101 | 1562.5   |  kHz |
+|  0110  | 781.25  |  kHz |
+|  0111  | 390.625 |  kHz |
+|  1000 | 195.312  | kHz |
+|  1001  | 97.656  | kHz |
+|  1010  | 48.828  | kHz |
+|  1011  | 24.414  | kHz |
+|  1100 | 12.207  | kHz |
+|  1101 |    6.103 |  kHz |
+|  1110 |    3.052  | kHz |
+|  1111 |    1.526  | kHz |
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