Implicit clocks and resets
In most (currently all modules written), we only use one clock and one reset signal. Even if clocks and resets may vary across designs, almost all individual modules would only use one.
Therefore, having to be explicit about clock and reset signals for reg declarations is a bit pointless most of the time.
If we know an entity/pipeline only has one clock, we could infer it from context, and thus reduce register declarations to
reg val reset rst = expr;
Implementation considerations:
- Clocks for most modules is easy to infer. If the module head only has one input with the
clk
type in its head, the signal can be made implicit. - Resets (which are currently untyped
bool
) are harder, but would be made easy if we add a separatereset
type. This is probably a good idea most of the time anyway, because resets are special and you probably don't want to do arbitrary computations on them by accident. - Do we also want to infer the clock signals for entities and pipelines which take clocks? If so, we might need new syntax to separate (possibly implicit) signals from normal arguments
- Looking at the
head
is not always enough. If more than one clock or reset is involved, those will be defined inside a module, which means clock inference must be disabled if more than one clock/reset appears in an entity/pipeline body. This means doing clock inference after type inference
Also, if we start adding domain checking, we want to be implicit about clocks and resets too, so this might be a first step towards that, or be an integral part of that system
Edited by Frans Skarman