Lab-1:-Vivado-Design-Flow-for-a-Simple-PS-Design.md

-
 # Lab 1: Vivado Design Flow for a Simple PS Design
 
 ---
@@ -317,18 +316,19 @@ We will connect to the remote Zedboard setup through a Hardware Server. We need
    |------|---------------|
    | Target Name | SMR3557_ICTP |
    | Type | Hardware Server |
-   | Host | <IP assigned to you> |
+   | Host |  |
    | Port | 3121 |
 
-
+   ```plaintext
    Leave the rest of the options by default. Click "Ok".
-
+   ```
 3. You may receive the following error message:
 
    ![image](uploads/1e668d5e82e53253581927ab08bc9980/image.png)
 
+   ```plaintext
      Dont panick, for security reasons "Ping" is disable of our hw_servers, and that is why you may see this error. Click           Yes to save the connection settings. 
-
+   ```
 4. You should see the following window:
 
    ![image](uploads/7cae96048b04afb0544925eef96e8674/image.png)
@@ -341,10 +341,10 @@ We will connect to the remote Zedboard setup through a Hardware Server. We need
    | Debug Type | Standalone Application Debug |
    | Connection | SMR3557_ICTP |
    | Hardware Platform | lab1_hw_wrapper_hw_platform_0 |
-   | Bistream File: | <Empty for this example> |
+   | Bistream File: |  |
    | Initialization File | ps7_init.tcl |
-   | FPGA Device | <To be selected in the next step> |
-   | PS Device | <To be selected in the next step> |
+   | FPGA Device |  |
+   | PS Device |  |
 
    ![image](uploads/6567e3c6737ef85d6e1e22ff392a186b/image.png)
 7. Click **Select** in the **_FPGA Device_** option and **unmark** the **Auto Detect** option to see the available list of FPGAs connected. Choose the one assigned to your group and select the **xc7z020** option, and click OK.