# Lab 1: Vivado Design Flow for a Simple PS Design
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Prepared by:
C. Sisterna & M.L. Crespo
ICTP-MLAB
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# Before Starting:
Be sure to **pull** the latest version of this Lab from the git folder. If you haven't created it yet, you can follow the steps detailed in this [guide](https://gitlab.com/smr3562/labs/-/wikis/How-to-install-Git-and-clone-the-project)
**If you are having problems connecting, please be sure to check the [How to connect to your remote lab setup](https://gitlab.com/smr3562/labs/-/wikis/How-to-connect-to-your-remote-labs-setup) guide._
**Note**: a pdf version of Lab1 is available [here.](https://gitlab.com/smr3562/labs/-/raw/master/Labs/Lab1_HELLO_WORLD/pdf/Lab-1_-Vivado-Design-Flow-for-a-Simple-PS-Design.pdf?inline=false)
## Section 1: Vivado Design Flow for a PS Based Design
### Introduction
This lab guides you through the process of using Vivado Development Suite to create a simple SoPC design targeting just the PS part of the Zynq-FPGA in the ZedBoard. You will create the board design in the Vivado IP Integrator, to export it to the SDK tool, generate the board support package (BSP), and use an already done template to display the “Hello world” string in a console.
### Objectives
After completing this lab, you will be able to:
- Create a Vivado project based on the IP Integrator
- Add and configure the PS7
- Generate HDL wrapper
- Export the design to SDK
- Create an application project in SDK, creating a board support package and ‘C’ code
- Configure the UART to communicate the PC with the ZedBoard
- Program the PS7 using the .elf file
- Execute the ‘C’ code in the processor
### Description
The design consists of creating a simple project in which the PS7 will be configured to communicate with the PC to display the ‘Hello World’ string.
## Design Flow
According to the presentation in class the flow detailed below should be followed in
**Following is a resume about each of the processes in the above flow towards this Lab**:
**1.** The design and implementation flow begin with launching Vivado. Within Vivado
the entire design, from creating a block diagram to generate the bitstream, is
carried out.
**2.** Open the **Create New Project Vivado** option.
**3.** From Vivado GUI, select **Create Block Design** to launch **Vivado IP Integrator**. Add the
**ZYNQ7 Processing System IP** to include the ARM Cortex-A9 PS in the project.
**4.** Double click on the **ZYNQ7 Processing System** block to configure the PS settings to
make the appropriate design decisions such as selection/de-selection of dedicated
PS I/O peripherals, memory configurations, clock speeds, etc.
**5.***At this point, you may also optionally add IP from the IP catalog or create and add
your own customized IP. Connect the different blocks together by dragging
signals/nets from one port of an IP to another. You can also use the design
automation capability of the IP Integrator to automatically connect blocks together.*
**6.** When finished, generate a top-level HDL wrapper for the system.
**7.***When a project is created by defining a board, e.g. ZedBoard, a default constraint
the file is added to the project. This .xdc file defines the association between the FPGA I/Os and the peripherals existing in the ZedBoard. In the case of using an FPGA I/O that is not associated with any peripherals, e.g. the JA1 PMOD connector, a customized .xdc file has to be added to the project. If there is any signal coming from the PL section to an I/O pin that is not defined in the .xdc file, then the tools will generate an error during the bitstream generation. Hence, in case needed add a Xilinx Design Constraints (XDC) file to the Vivado project.*
**8.***Generate the bitstream for configuring the logic in the PL, if soft peripherals or
other HDL are included in the design, or if any hard peripheral IO (PS peripheral)
were routed through the PL. The PL part of the FPGA can be configured from
either from SDK. The configuration from the SDK is the most commonly used.*
**9.** Once, the hardware portion of the embedded system design has been built, export
the design to the SDK to create the software design. A convenient method to
ensure that the hardware for this design is automatically integrated with the
software portion is achieved by Exporting the Hardware. File -> Export -> Export
Hardware. Assure to check the “Include Bitstream” option.
**10.** Launch SDK. **File -> Lunch SDK**.
**11.** Within the SDK, for a standalone application (no operating system) create a Board
Support Package (BSP) based on the hardware platform and then develop your
user application. Once compiled, a *.ELF file is generated.
**12.** Create a new ‘C’ application (usually from the available templates).
**13.** Write your own ‘C’ code according to the requirements of the project.
**14.***In case there is logic in the PL part of the Zynq, it is needed to configure the FPGA
with the respective .bit file.*
**15.** Execute the **Run on Hardware (Debug)** process to program the PS part of the Zynq
with the respective *.elf file, and automatically execute the ‘C’ code in the
processor.
**Note:***the steps of the flow design printed in italic are steps that are not necessary in
this lab, but will be used in following ones.*
## Create a Vivado Project
**Objective:** Execute Vivado and create a PS7 based project targeting the ZedBoard.
**1.** Open *Vivado Design Suite*.
**2.**  From the **Quick Start** menu, click **Create Project** to start the wizard or click **File → Project → New**.
You will see **Create A New Vivado Project** dialog box in the **New Project** window. Click **Next**. Use the information in the table below to configure the different wizard options:
| | Create Project Subdirectory | Do not check this option. |
| Click **Next** | | |
| Project Type | Project Type | Select **RTL Project**. Keep do not specify sources at this time box unchecked |
| Click **Next** | | |
| Add Sources | Do nothing | |
| Click **Next** | | |
| Add Existing IP | Do Nothing | |
| Click **Next** | | |
| Add Constraints | Do Nothing | |
| Default Part | Specify | Select **Boards** |
| | Board | Select **ZedBoard Zynq Evaluation and Development Kit** |
| Click **Next** | | |
| New Project Summary | Project Summary | Review the project summary |
| Click **Finish** | | |
After clicking **Finish**, the **New Project Wizard** closes and the project just created
opens in the Vivado main GUI.
The board selected during the project creation, in this case, the **ZedBoard**, has a
direct impact on how the **IP Integrator**, within the **Vivado**, executes.
**Vivado IP Integrator** is board aware and it will automatically assign dedicated Zynq IO
ports to physical pin locations mapped to the specific board peripherals when
the **Run Connection** wizard is used.
Besides doing I/O pin constraints, **Vivado IP Integrator** also defines the I/O standard (LVCMOS 3.3, LVCMOS 2.5, etc) to each IO pin; saving time for the designer in doing so. Therefore, the XDC file (the Xilinx Constraint File, .xdc) associated with the pre-defined IO pin locations is not required from the user when the design uses only the defined ZedBoard peripherals.
Note: in other labs you will learn how to add a specific .xdc file.
**3.** The **Vivado Design Suite** main window should look like the following figure:
**4.3.** You can design a new embedded system in **Vivado** using **IP Integrator** by
adding a **ZYNQ7 Processing System** block. By adding this block, you can configure
one of the ARM Cortex-A9 processor cores for your application. You can also place
additional IP blocks to increase the capabilities of the embedded system.
To insert a **ZYNQ7 Processing System**(PS7) block you can either click the **Add IP**
icon or  do a right-click on the canvas blank space and select **Add IP** from the available options.
**4.4.** A small window will come up showing the available IPs (that is, they are the
**Intellectual Property** cores, **IP**, that are already available. We will see later, in other labs, how to create and add our own IP. To search and add the **PS IP** core, we can
either scroll down to the very bottom of the IP list or search the IP using the
keyword **zynq**. Double click on the **ZYNQ7 Processing System** IP to select and add it
to the canvas.
**5.** The **Zynq7 PS** IP block is placed in the block diagram canvas. The I/O ports shown
**Objective:** Customizing the Zynq Processing System settings. For this particular Lab many of the default settings of the PS7 will not be necessary, therefore they will be modified in the following steps.
**9.** Double click in the **Zynq7 PS** block to open the customization window (see figure
below). In this window the **Processing System** part of the **Zynq** device can be
Leave the **Include Bitstream** box *unchecked* since there is no logic in the PL to be configured. Click **Save** in case you are asked. Also, leave the **Export** option with the
default directory that is shown. Click **OK** to continue.
Note: you *might* get an error message similar to this:
**Objective:** Executing the ‘C’ application in the Zynq.
**1.** On the **Project Explorer** pane, select the **hello_world** application, and then right-click mouse and select **Run As -> Launch on Hardware (GDB)**.
