Release Notes for ska-mid-cbf-tdc-correlator-v0.2.0 =================================================== Date and time generated: 2023-02-02 23:34:15.325304 Summary ------- * SPFRX packetizer now used for BITE. * Add Wideband Input Buffer and Packet Stream Repair modules. * Return both of the cross-polarisation visibilities (XY and YX) for auto-correlation. * Added Histogram modules before the VCC channeliser, resamplers, 16k channelsiers, corner turners. * VCC and 16k Channelsiers overhaul. * Scaling and shifting order reversed to scale first, then shift so can use whole range. * Resampler has added timestamp gap detection * Connect RDMA port to fsp_streams (other side of FS_transport) so can collect data from any frequency slice * Convert timestamp in samples since the epoch to seconds+fraction since epoch. Fixes ----- * Serial Lightweight Interconnect Mesh (SLIM) links working. * Empty and Full edge cases for blockram corner turner. * Long Term Accumulator (LTA) programming bugs. * Lengthen hysterisis time for the write_status/antenna_active register status signal. * Corner Turner reset sequencing. * 16k channelsier reset after resampler stops. * Channel labeling out of 16k channeliser. Register Changes ---------------- * LSTV gains Address allocation registers. * BITE FIR filter implementations made to use same regsiter definition. * BITE tone gen updated. * Corner Turner cell_size and num_sample_groups registers added. * Resampler has added timestamp gap detection register status bit * Default to serial_loopback_enable = True on register reset Changelog - Commit Messages --------------------------- Automatically generated changes since the last version (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1) according to commits. Commits filtered by files used in the build. For repository talon_dx at path . ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Fix some quartus warnings. Missing pin constraints, undriven debugaccess port. * Assign AXI master high order w.strb bits explicitly to quiet quartus warning. * Fix LEAP/MBO comments. EMIF user reset distribution and flops added. Unused AXI master wdata bits tied to '0'. * Reduce reported SLIM transceiver from 26 to 25 Gbps - matching the achieved data rate (sans 66/64b coding). * fix synthesis message for when creating hyper register timing constraints. * Update the transciever PMA settings - swap pre and post tap values. * Output Swing Level (VOD) = 19 (was 20) * Pre-Emphasis First Pre-Tap Magnitude = -6 (was -2) * Pre-Emphasis First Post-Tap Magnitude = -2 (was -6) * Merge branch 'slim_updates' into 'master' * SLIM MBO updates * See merge request SKA/TalonDX/FW/talon_dx!12 * Add missing reset false_path constraint. * Change MBO numbering to match the FCI leap numbering scheme (not the schematic). * supply default for AXI buses' w.id value - quartus warning. * Assign AXI master signals default values to quiet warnings. * Fix Critical Warning for unused transceivers, Adjusted TX PMA analog settings, enabled staggered power on reset release for transceivers. Cosmetics. * Remove rx_fifo_ready gating - signal tap shows that it does nothing useful. * Use 'rx_fifo_ready' signal from the transceiver to prevent the SLIM module from underrunning the RX FIFO. * Split the SERDES reset into separate TX and RX, so that TX can be reset before RX. * The RX reset sequence requires that the PMA lock to data. This could be causing a race condition if the TX is also resetting at the same time, or occurs after rx completes its reset. * Update talon_status.sdc * Upgrade IP (HPS, EMIFs) to quartus 22.1. Expand TR EMIF to 256GB. Travel flopped resets out of EMIFs. * Zero out the detri address table. * Merge branch 'talon_status_constraints' into 'master' * WIP: Talon status constraints * See merge request SKA/TalonDX/FW/talon_dx!10 * Added constraints for Talon Status * Merge branch 'talon_status' into 'master' * added _atxpll_locked_ and _atxpll_cal_busy_ signal outputs for talon_status * See merge request SKA/TalonDX/FW/talon_dx!9 * Update talon_dx_top.vhd * connected EMIF pll_locked signals * Update talon_dx_top.vhd * connected EMIF pll_locked signals * added _atxpll_locked_ and _atxpll_cal_busy_ signal outputs for talon_status * get the specific $revision.json file, rather than any one that sort of matched. * Comment out some unused ddr memory pin locations. Uncomment Preserve_unused_xcvr_channel assignments. Hopefully eliminate some warning messages. * Update create_revision.py script to make it possible to create a revsion with jsut a base image (no persona). * Add timing constratins for pin o_fan_full_speed_n. For repository DeTrI at path ../DeTrI ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Increase maximum number of DeTrI endpoints to 256. * As required by the 8-receptor tdc_vcc_processing persona build. For repository bite at path ../bite ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * CIP-1223 Pass Address allocation geneics down to LSTV. * Replace dish_pkt_gen with upgraded LSTV_replay and SPFRX_packetizer. * update to use dish_pkt_gen2 that uses the spfrx_packetiser. For repository bite_fir_filter at path ../bite_fir_filter ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Merge the register definitions of the two FIR filter implementations. * Apparently the ena port direction is changeable on the quartus native DSP block. Fixing timing bug caused by the consequential misswiring of vld => ena(2) instead of ena(0). * Upgrade bite_fir_filter.json and registerDef outputs * Fix bug in bite_fir_filter2 coefficient loading that would effectivly only give you the sign of the coefficient. For repository bite_tone_gen at path ../bite_tone_gen ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * upgrade bite_tone_gen.json and registerDef outputs. For repository blockram_corner_turner at path ../blockram_corner_turner ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Correct edge cases for empty and full. * Simplification of empty and full indicators. * Adjust buffer level logic so goes not empty when entire first row is available. Goes empty when try to read past a row that has not been completely written yet. * Explicitly one extra flop in the address_permuter when g_ATOM_SIZE = 2, else (when g_ATOM_SIZE > 2) a variable lateny pipeline hyper register. For repository circuit_switch at path ../circuit_switch ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ No commits recorded since the last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1). For repository correlator at path ../correlator ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Fix Auto-correlation congegation of cross correlation products. * The conjugation was selecting the wrong range of bits to negate including some of the least significant bits of the real component. * TB now simplified - since no special case for auto correlations. * Update IP to quartus 22.2 * Update to return both of the cross-polarisation visibilities for auto-correlation. * Previously one was returned as zero. * Now computed as the conjugate of the other. * Costs a few more resources and maybe timing, but makes output more consistent. * Update comment on cmac-quad readout * Add condition to LTA FSM to sip writes when nothing yet to write. Fixes issue where the LTA gets stuck when the first data-frame is the null data-frame. * Update and fix LTA testbenches. * Fix LTA programming bug that prevented programming through the DDR arbiter. * LTA waiting for wait_req = '0' which does not happen until a write request. Made TB simulate this behaviour. * Fix bug in register field fifo_baselines_to_full * Update intel floating point IP to version 19.1.2 (from Quartus 22.1) * Update version in mta register json, update registerDef output products. For repository ddr4_arbiter at path ../ddr4_arbiter ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Add missing signals to o_to_user. * Quiet quartus some. For repository ddr4_corner_turner at path ../ddr4_corner_turner ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Fix short hysterisis time for the write_status/antenna_active register status signal. * Add pipeline stage to blockram_corner_turner_wrap so can distribute the reset signal for better timing. * Added cell_size and num_sample_groups registers * Update arbiter fsm state names to coding standard. * Check only on the start of a frame for the timestamp to be a multiple of g_NUM_SAMPLES_TO_COLATE. * Refactor some signal names and add some comments to read address generation. * Add g_NUM_SAMPLES_TO_COLATE (=4) to remove a magic number. * Adjust start of frame dropping for start timestamp. * Apply FFT shift to the channel group output of the block RAM corner turner. * Convert flagged data to most-negative at the CDC input buffer. * Simply reset sequence - reset until a start of frame. Drop data valid until timestamp multiple of 4. * Clean up some constants. * Change counting of loaded timestamps at startup of blockram corner turner. * Some tidyup of code. No functional change. * Add channel_group last signal, use that in the input buffer to align groups into CDC fifo. Fix clock domain of addr calc. * May fix odd timestamp capture. * Add recovery mechanism to find a timestamp header if FSM gets out of sync with FIFO. Tidy of code. * Move CT write address generation into the input buffer. * The separate timestamp_to_wraddr module timing depended on the CDC buffer taking at least as long to ouput the data after providing the timestamp and channel group (5 cycles). * Flop write_timestamp register read fields. If antenna not used report write timestamp as all '1's. * register version set to 1.0, update registerDef outputs. * Fix synthesis error in corner_turner_status. Was using variables for counter registers - should be signals. * Other tidyup to use unsigned types instead of jumping though hoops to use std_logic_vectors. For repository dish_pkt_cap at path ../dish_pkt_cap ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Upgrade registerDef json and generated vhdl pkg. For repository dish_pkt_gen at path ../dish_pkt_gen ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ No commits recorded since the last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1). For repository dsp_lib at path ../dsp_lib ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Merge branch 'master' of gitlab.drao.nrc.ca:SKA/util/dsp_lib * Adding 2-dimensional array. * Merge branch 'master' of gitlab.drao.nrc.ca:SKA/util/dsp_lib * Adding WIDE stream. * Add chg_last (channel group last) flag to t_CT_STRM. For repository ethernet_100g at path ../ethernet_100g ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Add flops to reset to improve distribution and ease timing. * added o_tx_pll_locked and o_tx_pll_cal_busy signal outputs for talon_status * Update registerDef output products. Update json format. For repository gaussian_noise at path ../gaussian_noise ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Added g_CEIL_LOG2_MIN_PERIOD to extend the period of the random number generators. * Upgrade gaussian.json and registerDef outputs. For repository histogram at path ../histogram ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Newly added. Last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1) not found in this repository. For repository ic_ch16k at path ../ic_ch16k ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Adjust the register bus address range to be only that required (15b instead of 16b). Also add reset flops for heriarchical duplication in quartus. * Flop and distribute reset. * Mojor Update 20230118 * Detangling Clipping flag in Scaling * Label the channels correctly, rather than just in the order they come out. For repository jlib at path ../jlib ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ No commits recorded since the last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1). For repository led_ctrl at path ../led_ctrl ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Updgrade registerDef JSON. For repository lstv at path ../lstv ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Increase in reset pipelining as suggested by Quartus report for avaiable reset heirarchy. * CIP-1223 Add registers for the allocated start and end addresses, and the current write address for progress monitoring. * Updated regdef json file format. * Fix readback of enable_resampler_dithering register field. For repository lstv_replay at path ../lstv_replay ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Get running in testbench. * Initial rewrite to connect directly to spfrx_packetizer. For repository packet_stream_repair at path ../packet_stream_repair ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Newly added. Last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1) not found in this repository. For repository polarization_coupler at path ../polarization_coupler ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Update register json and registerDef output products. For repository rdma at path ../rdma_64b ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * CIP-1215 Fix packet dropping logic. * It was occasionally letting the first word through, which would fill up the store and forward buffer, resulting in it pushing backpressure and ultimately stopping all RDMA traffic. * Upgrade Register def outputs. For repository resampler_delay_tracker at path ../resampler_delay_tracker ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Add pipeline for stream gap checking. Fortify polarisation muxing logic. * Replace variable latency hyper-pipelining with regular pipelining. Avoids problem where pols outputs get out of sync when they have different pipeline delays. * Change o_reset_downstream to strobe on the falling edge of run. * Add some pipeline stages and manual reset distribution to improve timing. * reset start of stream flag when starting the resampler so that can recover from a timestamp gap. * Temporary fix for 16k channeliser bug - export a reset signal when RDT not running. * Update resampler_delay_tracker_dual_pol.vhd * Added timestamp gap detection register status bit * Add version to fodm registers. Update registerDef output products. For repository slim at path ../slim ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Fig bug in tx_serial interconnect when Hard PCS enabled. * Pipeline mismatch between data and valid, so some words missed. * Expanded testbench for framer_mac_pcs_tb to support hard-PCS. * Default to serial_loopback_enable = True on register reset. * This is to ensure that the trancseiver receive data-path has a valid input signal after startup, which will help protect it when not in use, and doesn't have a valid signal comig in. It should also help reduce power usage as it can complete its PLL locking and equalisation functions. * Tidy up. Convert user_idle_word to unsigned type. * Prevent transciever from overflowing its RX core FIFO and locking up. Gate on block aligned, but keep reading from FIFO. * Solves startup issue where random control that looks like many small packets to the MAC which causes backpressure that overflows the rx FIFO. For repository spfrx_common at path ../spfrx_common ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Newly added. Last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1) not found in this repository. For repository spfrx_packetizer at path ../spfrx_packetizer ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Newly added. Last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1) not found in this repository. For repository sys_id at path ../sys_id ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Fix Quartus warning. For repository talon_status at path ../talon_status ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Newly added. Last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1) not found in this repository. For repository tdc_base at path ../tdc_base ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Reconnect o_qsfp_mod_sel_n port. Don't know why it was disconnected. * Add missing debugaccess port to jtag_blaster to eliminate quartus warning. * Additional travel flop for 100GbE rx stop signal * Add FW for JTAG via DeTrI. Requires some software to make active. Currently disabled. * Update comments on which MBOs connect to which transceivers and FCI-LEAP modules. * Add reset generation logic for clk _125, pass to MBOs * cleaning up SLIM status bit mappings tabs * cleaning up SLIM status bit mappings * removed old talon_status module and integrated new talon_status module * Add EMIF resetting from Talon_status registers to initiate re-calibration. For repository tdc_vcc_processing at path ../tdc_vcc_processing ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Connect RDMA port to fsp_streams (other side of FS_transport) so can collect data from any frequency slice instead of only the hard-wired first. * Connect post_vcc_histogram to other end of travel flops to improve timing. * explicity set `o_to_emif_lta.local_reset_req <= '0'` to elimintate quartus warning. * Reverse the rx_meta_vis array order to be downto. * Matching change made in the visibility_pkt_streams_to_ethernet, to make consistent. * CIP-1223 Allcoate LSTV ddr address space from 2GB to 32GB. * Add conditional generate statement to only include the packet merge module if there is more than 1 rdma stream to merge. * Reset the 16k channeliser after the RDT stops. * Speedup (double) the maximum read rate from the corner turner. * Config 4 FSP chains. Manual 450 clk distribution. * Temporary fix for 16k channeliser bug - export a reset signal from the RDT and reset the 16k Chan when RDT not running. * Fix reset from wrong clock domain. * Add Wideband Input Buffer and Packet Stream Repair * Upgrade histograms to independent dual pol. Channelsier gain programming working. * Update VCC CH20 entity instantiation. * Update corner turner generic assignments. * Move historgrams to the light-weight DeTrI bus. * Histogram didn't like being on the 64b bus - problem with DeTrI register bank maybe? * Add Histograms to datapath, accessed from the HP DeTrI bus. * BITE and CT moved to DDR that pass calibration. * TR does not pass currently. * Swap LTA/BITE emif (formerly top right) with Corner Turner 1 emif (formerly bottom right). For repository vcc_ch20 at path ../vcc_ch20 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Adjust the register bus address range to be only that required (5b for 21 registers instead of 9b/16b). * Major updates In 202301-22 * Detangle Clipping Flags VCC_CH20_IP_FS_Scale.vhd * Update DeTrI Avalon bridge connections. Remove DeTrI CDC. For repository visibility-packetiser at path ../visibility_packetiser ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Switch input array order of visibility_pkt_streams_to_ethernet to be downto. * To reduce confusion when connected to slim links that are also a downto direction. * Update IP to quartus 22.2 * Add 20 explicit flops before timestamp divider instead of hyper-registers. Seems to work better unfortunately. * Use hyper-registers to pipeline the timestamp divide operation. * Convert timestamp in samples since the epoch to seconds+fraction since epoch. * Compute the channel_id according to the channel_count. * Update intel floating point IP to 19.1.2 (Quartus 22.1) For repository wideband_input_buffer at path ../wideband_input_buffer ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Newly added. Last version tag (ska-mid-cbf-tdc-correlator-v0.1.0-rc.1) not found in this repository. For repository wk_lib at path ../wk_lib ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ * Create altera megafunction implementation for stratix10 simple dual port RAM. * Extend from_ohot function to accept up to 256b slvs, p_sum_carry proicedure rewritten and signed version created. * Explicitly assign varaible to don't care in header_prepend module. * Reduce quartus warning. * Hyper registers get g_MIN_CYCLES before or after depending on whether retimeing forward or backwards. * Cleanup sdc constraints - get register collection once and store in a variable. * Add optional ingress fifo to AXI4 Bytise modules for when a longer stop latency is required. * Add missing from_slv with valid function for AXI4_streaming_1024_t * Add taps for more LFSR lengths. Adding 68-768,1024,2048,4096. * Added to stratix10 dc fifos the VERIFIED_GRAY_CODED_BUS_DESTINATIONS assignment - new in quartus 21.3. * re-generated emif_pkg.vhd * Merge branch 'talon_status' into 'master' * Talon status * See merge request SKA/util/wk_lib!3 * Allow zero as a valid argument to misc_tools_pkg.ceil_log2(), return 0. * Allow zero as a valid argument to misc_tools_pkg.ceil_log2(), return 0. * Fix type missmatch on keep for single bit SLV AXI4-streaming_8_t.keep. * Add AXI4_Streaming_1024_t definition to AXI4_pkg.vhd. * Updated pkg with latest VHDL_record_code_generator.py * added pll_locked signal to t_from_EMIF record for talon_status * Update emif_pkg.vhd Commit Hashes ------------- * talon_dx: 818f1da4a3735d2b779bc29b8901f2f1067b2b18 * DeTrI: 76f61c546b53ffcbf3d5b12207879651ccd01bfb * bite: a19799afedaf4f99d4db63dcc6336bd76c8e326c * bite_fir_filter: 575a39db2c5bba66e236ad96e452066e263e33e3 * bite_tone_gen: 175d97975876b7aac8e671158eb02d02cace4132 * blockram_corner_turner: 5deaa7a22c5dfa3415bf21e4cb25c0cd5fab0a05 * circuit_switch: c05bdc9778baab0a1fc128a6ee865a5bc4f94946 * correlator: 7d5d4a97ae72f3447ad7b6c704847408679b8f2d * ddr4_arbiter: ca7524f484c6538239196589d44a49c3d0cb52e8 * ddr4_corner_turner: ba50ae2283b5f15b0326a7f533686510fe7d696b * dish_pkt_cap: e41b3e7e797614d517458fdb76b17979a7432c08 * dish_pkt_gen: 63880021ea7fbbd3311f064df6bb43c1a8cd6897 * dsp_lib: febed658fcb11efb5092bd0e9919f4c7cd39f907 * ethernet_100g: 7fb7a6efea03a629c68b69a305d79d5b1508150a * gaussian_noise: 9c337a516649818cdf344250aff271b9ae082fcf * histogram: 0fa23ddde1b308851b9b394a54c0dd604a5e4578 * ic_ch16k: 25d66c3c94856e728b265aa6ca68603f6e984d60 * jlib: 763ba1f6b6a1c13684df9d4d6ea935978e0d13bb * led_ctrl: eb9d3d2376a1df89636913129161cb619e6441dd * lstv: cb076cffcd8045cf627f1787922b98a39f167756 * lstv_replay: f05efb1790fe8032d1605ee7e3df61699fd96eb2 * packet_stream_repair: 29a6087a5de233563c61f0a39988dcc264cce02b * polarization_coupler: 14ccae4043da377ed56e68d90e6860b48a189cda * rdma: 9d3da058c815ca16db3fb4cdab94685c7e2f9d23 * resampler_delay_tracker: 72574922efeb57c483a6c89c9c7ddbef080cae1f * slim: d036e18552898a41690b826c17208864dff31e87 * spfrx_common: 0d2f9e294546eceefaef6377f6a4e5953e7ffa3f * spfrx_packetizer: 64afb7670975506add2fe79c113aeec99550d87d * sys_id: a728de41d4fbb2618801471d9fae9380de4bfadf * talon_status: 3c0a7dc91d10d8b0c77d11e801ab914d8e409124 * tdc_base: d98482226f65466741daddd3573723f2eda8bd83 * tdc_vcc_processing: 1bcc7068a661c33700b9693d46479d1627334d0e * vcc_ch20: e07873077048282100b5bc3528dea9391997bc9f * visibility-packetiser: 552548694c7d4ad6a8910352b335ab613ab36ad9 * wideband_input_buffer: 7c3f4187c9f8bf3abdec1af878ccc380647b1baf * wk_lib: 422a15f544e46d9947a775fa88183ff69413a20f