coherence support for l1dcache_vipt
This requires the following:
-
OpenSmart to be setup. -
design of the controller. Need to identify the request patterns and scenarios -
Need to make the tag and data-rams as dual-ported. -
MSI states need to be maintains along with the TAGs in the SRAMs and Fill-buffer. -
Expected that the transient states of MSI will be present in the fill-buffer. This needs more evaluation and study to decide. -
Use a custom test-bench with behavioral L2 for testing. This will require the test-bench to generate custom/arbitraty transaction/traffic to robustly verify the design. Challenge here would be to have golden trace to automate verification.
Edited by Neel Gala