Difficulty in compiling "make CONFIG=soc_config.inc generate_verilog"
We are facing difficulty in executing the commands for simulating the core.Our bluespec directory is initialised, our DTC version is 1.5.0. We are attaching the logs belowlog.txt
We are facing difficulty in executing the commands for simulating the core.Our bluespec directory is initialised, our DTC version is 1.5.0. We are attaching the logs belowlog.txt