Trigger Module is a non-building stub; match logic is execute-only (no data-watchpoints)
Summary
With no_of_triggers > 0, c-class does not build; and even with the build fixed, the trigger match logic supports instruction/PC triggers only — no load/store data-watchpoints. (Found while integrating c-class RV64IMAC with an external Debug Module.)
Build failure (config-only enable does not compile)
Setting triggers / trigger_num=4 and running make generate_verilog:
Error: "src//stage1.bsv", line 129, column 32: (P0145)
Preprocessor macro `Breakpoint' is not defined
BSC COMPILE ERRORNo Verilog is produced. Three distinct defects:
- Compile abort —
stage1.bsv:129references theBreakpointmacro, which is defined intrap.defines:5but not on stage1's include path. - No indexed-CSR generation —
csrbox/csr_gen.pyhas no support for indexed CSRs, but the trigger CSRs (tdata1/tdata2, selected bytselect) are inherently indexed, so they cannot be emitted. - No CSR→stage1 wiring — there is no connect block in
riscv.bsvrouting the trigger CSR file to thestage1match logic.
Match logic is execute-only (even once it builds)
The match block (stage1.bsv:139-147) gates only on mc.execute (compares PC or instruction word). mc.load / mc.store are declared (ccore_types.bsv:747-749) but never referenced — and check_trigger runs in the fetch stage (only pc/instr are available), so the effective data address (computed in the memory stage) cannot be matched. Data watchpoints (break-on-access-to-address) are therefore absent and would need a memory-stage match path.
Expected
A buildable RISC-V Trigger Module (mcontrol6) supporting execute triggers and load/store data-watchpoints.
Suggested fix
Fix the Breakpoint define path; add indexed-CSR generation to csr_gen.py; add the riscv.bsv connect block; and add a memory-stage data-match path (effective-address/data comparator + tdata2 routing + ordered trap injection) for watchpoints.
Question
Is the Trigger Module intended to be functional in c-class, or is it known-incomplete? Happy to help test a fix.