@@ -26,7 +26,7 @@ ETS provides greater time resolution by acquiring sampling points between the sa
ETS sampling is available on both analog inputs (CH1 and CH2). However the trigger source for ETS sampling is available only from CH1 and it is possible to adjust only the trigger voltage (but not trigger hysteresis or slope).
Implementation is achieved with the help of tapped LUT delay line inside the FPGA which provides exact time of sampling point relative to sampling clock.
Implementation of ETS is achieved with the help of tapped LUT delay line inside the FPGA which provides exact time of sampling point relative to sampling clock.
