Commit ba0692c3 authored by Dejan Priversek's avatar Dejan Priversek
Browse files

FPGA: add generator phase, modify timebase coding, compress fpga.bin

parent 17b76b9f
......@@ -22,3 +22,4 @@ set_property CFGBVS GND [current_design]
set_property CONFIG_MODE S_SERIAL [current_design]
set_property BITSTREAM.CONFIG.PERSIST NO [current_design]
set_property BITSTREAM.STARTUP.STARTUPCLK CCLK [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
\ No newline at end of file
......@@ -56,6 +56,7 @@ set_false_path -from [get_pins sig_out_enable_d_reg/C] -to [get_pins signal_gene
set_false_path -from [get_pins sig_out_enable_d_reg/C] -to [get_pins signal_generator_inst/generator2On_d_reg/D]
set_false_path -from [get_pins generator1On_reg/C] -to [get_pins signal_generator_inst/generator1On_d_reg/D]
set_false_path -from [get_pins generator2On_reg/C] -to [get_pins signal_generator_inst/generator2On_d_reg/D]
#AWG inputs
set_max_delay -datapath_only -from [get_pins {generator1Delta_reg[*]/C}] -to [get_pins {signal_generator_inst/generatorDelta_1_i_reg[*]/D}] 2.000
set_max_delay -datapath_only -from [get_pins {generator2Delta_reg[*]/C}] -to [get_pins {signal_generator_inst/generatorDelta_2_i_reg[*]/D}] 2.000
......@@ -67,6 +68,7 @@ set_max_delay -datapath_only -from [get_pins {generator1Type_reg[*]/C}] -to [get
set_max_delay -datapath_only -from [get_pins {generator2Type_reg[*]/C}] -to [get_pins {signal_generator_inst/generatorType_2d_reg[*]/D}] 2.000
set_max_delay -datapath_only -from [get_pins {generator1Voltage_reg[*]/C}] -to [get_pins {signal_generator_inst/generatorVoltage_1d_reg[*]/D}] 2.000
set_max_delay -datapath_only -from [get_pins {generator2Voltage_reg[*]/C}] -to [get_pins {signal_generator_inst/generatorVoltage_2d_reg[*]/D}] 2.000
set_max_delay -datapath_only -from [get_pins {phase_val_reg[*]/C}] -to [get_pins {signal_generator_inst/phase_val_i_reg[*]/D}] 2.000
#clk_adc to clk_fx3 CDC
set_max_delay -datapath_only -from [get_cells {timebase_d_reg[*]}] -to [get_cells {timebase_dd_reg[*]}] 2.000
......
......@@ -240,6 +240,8 @@ architecture rtl of fpga is
--clk enable
generator1On : in STD_LOGIC;
generator2On : in STD_LOGIC;
phase_sync : in STD_LOGIC;
phase_val : in STD_LOGIC_VECTOR(bH downto 0);
--AWG1
genSignal_1 : out signed (11 downto 0);
ram_addrb_awg_1 : out STD_LOGIC_VECTOR (14 downto 0);
......@@ -565,6 +567,8 @@ signal generator1On : std_logic;
signal generator2On : std_logic;
signal sig_out_enable : std_logic;
signal sig_out_enable_d : std_logic;
signal phase_sync : STD_LOGIC := '0';
signal phase_val : STD_LOGIC_VECTOR(bH downto 0);
-- AWG custom buffer
signal wea_awg : STD_LOGIC;
......@@ -1139,6 +1143,8 @@ port map (
--Signal Generator(clk) enable
generator1On => generator1On AND sig_out_enable_d,
generator2On => generator2On AND sig_out_enable_d,
phase_sync => phase_sync,
phase_val => phase_val,
--AWG1
genSignal_1 => genSignal_1,
ram_addrb_awg_1 => addrb_awg,
......@@ -1533,6 +1539,7 @@ begin
mavg_enA <= cfg_do_B(9);
mavg_enB <= cfg_do_B(8);
when 28 =>
phase_val <= cfg_do_B(30 downto 16);
digitalClkDivide <= unsigned(digitalClkDivide_tmp);
when others => null;
end case;
......@@ -1602,64 +1609,50 @@ begin
timebase_d <= timebase; -- select sampling frequency for next frame
case timebase_d (4 downto 0) is
case to_integer(unsigned(timebase_d (4 downto 0))) is
when "00000" => -- 4 ns between samples
when 0 | 1 => -- 4 ns between samples
auto_trigger_maxcnt <= 400000; -- 1.6 ms auto trigger timeout
when "00001" => -- 8 ns
when 2 => -- 8 ns
auto_trigger_maxcnt <= 200000; -- 1.6 ms
when "00010" => -- 20 ns
when 3 => -- 20 ns
auto_trigger_maxcnt <= 100000; -- 2 ms
when "00011" => -- 40 ns
when 4 => -- 40 ns
auto_trigger_maxcnt <= 100000; -- 4 ms
when "00100" => -- 80 ns
when 5 => -- 80 ns
auto_trigger_maxcnt <= 100000; -- 8 ms
when "00101" => -- 200 ns
when 6 => -- 200 ns
auto_trigger_maxcnt <= 50000; -- 10 ms
when "00110" => -- 400 ns
when 7 => -- 400 ns
auto_trigger_maxcnt <= 25000; -- 10 ms
when "00111" => -- 800 ns
when 8 => -- 800 ns
auto_trigger_maxcnt <= 25000; -- 20 ms
when "01000" => -- 2 us
when 9 => -- 2 us
auto_trigger_maxcnt <= 10000; -- 20 ms
when "01001" => -- 4 us
when 10 => -- 4 us
auto_trigger_maxcnt <= 5000; -- 20 ms
when "01010" => -- 8 us
when 11 => -- 8 us
auto_trigger_maxcnt <= 5000; -- 40 ms
when "01011" => -- 20 us
when 12 => -- 20 us
auto_trigger_maxcnt <= 5000; -- 100 ms
when "01100" => -- 40 us
when 13 => -- 40 us
auto_trigger_maxcnt <= 5000; -- 200 ms
when "01101" => -- 80 us
when 14 => -- 80 us
auto_trigger_maxcnt <= 5000; -- 400 ms
when "01110" => -- 200 us
when 15 => -- 200 us
auto_trigger_maxcnt <= 2000; -- 400 ms
when "01111" => -- 400 us
when 16 => -- 400 us
auto_trigger_maxcnt <= 1000; -- 400 ms
when "10000" => -- 800 us
when 17 => -- 800 us
auto_trigger_maxcnt <= 500; -- 400 ms
when "10001" => -- 2 ms
when 18 => -- 2 ms
auto_trigger_maxcnt <= 200; -- 400 ms
when "10010" => -- 4 ms
when 19 => -- 4 ms
auto_trigger_maxcnt <= 100; -- 400 ms
when "10011" => -- 8 ms
when 20 => -- 8 ms
auto_trigger_maxcnt <= 100; -- 800 ms
when "10100" => -- 20 ms
auto_trigger_maxcnt <= 50; -- 1000 ms
--
-- the following capture speeds are not used
-- when "10101" => -- 40 ms
-- auto_trigger_maxcnt <= 20; -- 2 s
-- when "10110" => -- 80 ms
-- auto_trigger_maxcnt <= 10; -- 2 s
-- when "10111" => -- 200 ms
-- auto_trigger_maxcnt <= 10; -- 5 s
-- when "11000" => -- 400 ms
-- auto_trigger_maxcnt <= 5; -- 5 s
-- when "11001" => -- 800 ms
-- auto_trigger_maxcnt <= 5; -- 10 s
-- when "11111" => -- 2 s per sample
-- auto_trigger_maxcnt <= 100000; -- 1 ms auto trigger timeout
when 21 => -- 20 ms
auto_trigger_maxcnt <= 50; -- 1000 ms
when others =>
null;
end case;
......
......@@ -28,12 +28,15 @@ entity angle_gen is
bH : integer := 14; -- angle input precision high index
bL : integer := -17 -- angle input precision low index
);
Port ( clk : in STD_LOGIC;
clk_en : in STD_LOGIC;
generatorDelta : in sfixed(bH downto bL);
kot_gen : out sfixed(bH downto 0);
q_gen : out std_logic_vector(1 downto 0)
);
Port (
clk : in STD_LOGIC;
clk_en : in STD_LOGIC;
generatorDelta : in sfixed(bH downto bL);
phase_sync : in std_logic;
phase_val : in sfixed(bH downto bL);
kot_gen : out sfixed(bH downto 0);
q_gen : out std_logic_vector(1 downto 0)
);
attribute use_dsp48: string;
--attribute use_dsp48 of angle_gen : entity is "automax";
......@@ -53,7 +56,9 @@ signal next_angle : sfixed(bH downto bL):=to_sfixed(0,bH,bL);
signal quadrant : integer range 0 to 3 := 0;
signal generatorDelta_d : sfixed(bH downto bL):=to_sfixed(0,bH,bL);
signal generatorDelta_dd : sfixed(bH downto bL):=to_sfixed(0,bH,bL);
signal phase_val_d : sfixed(bH downto bL):=to_sfixed(0,bH,bL);
signal phase_val_dd : sfixed(bH downto bL):=to_sfixed(0,bH,bL);
signal phase_sync_d : std_logic:='0';
signal init_complete : std_logic:='0';
-- attribute strings
......@@ -79,34 +84,51 @@ begin
if (rising_edge(clk)) then
if clk_en = '1' then
-- register inputs
generatorDelta_d <= generatorDelta;
generatorDelta_dd <= generatorDelta_d;
kot_gen_tmp <= '0' & next_angle(bH-1 downto 0); -- angle output (0 to 2047)
kot_gen <= kot_gen_tmp;
q_gen_tmp <= std_logic_vector(to_unsigned(quadrant,2));
q_gen <= q_gen_tmp;
generatorDelta_d <= generatorDelta;
generatorDelta_dd <= generatorDelta_d;
phase_val_d <= phase_val;
phase_sync_d <= phase_sync;
if phase_sync_d = '0' and phase_sync = '1' then
curr_angle <= phase_val_d;
next_angle <= phase_val_d;
case phase_val_d(bH downto bh-1) is
when "00" => quadrant <= 0;
when "01" => quadrant <= 1;
when "10" => quadrant <= 2;
when "11" => quadrant <= 3;
when others => null;
end case;
else
kot_gen_tmp <= '0' & next_angle(bH-1 downto 0); -- angle output (0 to 2047)
kot_gen <= kot_gen_tmp;
q_gen_tmp <= std_logic_vector(to_unsigned(quadrant,2));
q_gen <= q_gen_tmp;
if (curr_angle(bH) = '1' and next_angle(bH)='0') or
(curr_angle(bH) = '0' and next_angle(bH)='1') then
if quadrant = 3 then
quadrant <= 0;
else
quadrant <= quadrant + 1;
end if;
end if;
if (curr_angle(bH) = '1' and next_angle(bH)='0') or
(curr_angle(bH) = '0' and next_angle(bH)='1') then
if quadrant = 3 then
quadrant <= 0;
else
quadrant <= quadrant + 1;
end if;
end if;
curr_angle <= resize( arg => curr_angle + generatorDelta_dd,
left_index => bH,
right_index => bL,
overflow_style => fixed_wrap); -- start from 0 if overflow
next_angle <= curr_angle;
curr_angle <= resize( arg => curr_angle + generatorDelta_dd,
left_index => bH,
right_index => bL,
overflow_style => fixed_wrap); -- start from 0 if overflow
next_angle <= curr_angle;
end if; -- phase_sync
end if;
end if; -- clk_en
end if;
end if;
end process;
......
......@@ -34,6 +34,8 @@ entity awg_core is
--clk enable
generator1On : in STD_LOGIC;
generator2On : in STD_LOGIC;
phase_sync : in STD_LOGIC;
phase_val : in STD_LOGIC_VECTOR(bH downto 0);
--AWG1
genSignal_1 : out signed (11 downto 0);
ram_addrb_awg_1 : out STD_LOGIC_VECTOR (14 downto 0);
......@@ -72,6 +74,8 @@ architecture Behavioral of awg_core is
clk : in STD_LOGIC;
clk_en : in STD_LOGIC;
generatorDelta : in sfixed(bH downto bL);
phase_sync : in std_logic;
phase_val : in sfixed(bH downto bL);
kot_gen : out sfixed(bH downto 0);
q_gen : out std_logic_vector(1 downto 0)
);
......@@ -119,6 +123,9 @@ signal dac_clk_buff_i_180 : std_logic;
signal generator1On_d : std_logic;
signal generator2On_d : std_logic;
signal generator1On_dd : std_logic;
signal generator2On_dd : std_logic;
signal s_axis_phase_tvalid_1 : std_logic;
signal s_axis_phase_tdata_1 : std_logic_vector(15 downto 0);
signal m_axis_dout_tvalid_1 : std_logic;
......@@ -200,6 +207,9 @@ signal random_num_2_tmp : signed (bH downto bH-11);
signal enable_rand_1 : std_logic;
signal enable_rand_2 : std_logic;
signal phase_sync_i : std_logic := '0';
signal phase_val_i : std_logic_vector(bH-bL downto 0) := std_logic_vector(to_unsigned(0,bh-bL+1));
-- set keep attributes for registers
--attribute keep: boolean;
--attribute keep of some_signal: signal is true;
......@@ -239,31 +249,39 @@ attribute KEEP of generatorDuty_2d : signal is true;
attribute ASYNC_REG of generatorDuty_2d : signal is true;
attribute KEEP of generatorCustomSample_2d : signal is true;
attribute ASYNC_REG of generatorCustomSample_2d : signal is true;
attribute KEEP of phase_val_i : signal is true;
attribute ASYNC_REG of phase_val_i : signal is true;
attribute KEEP of genSignal_1_tmp_d : signal is true;
attribute mark_debug of genSignal_1_tmp_d : signal is true;
attribute KEEP of dac_data_1 : signal is true;
attribute mark_debug of dac_data_1 : signal is true;
begin
angle_generator_1 : angle_gen
port map (
clk => clk_in,
clk_en => generator1On_d,
generatorDelta => to_sfixed(generatorDelta_1_i, bH,bL),
kot_gen => kot_gen_1,
q_gen => q_gen_1
clk => clk_in,
clk_en => generator1On_d,
generatorDelta => to_sfixed(generatorDelta_1_i, bH,bL),
phase_sync => phase_sync_i,
phase_val => to_sfixed(0,bH,bL),
kot_gen => kot_gen_1,
q_gen => q_gen_1
);
angle_generator_2 : angle_gen
port map (
clk => clk_in,
clk_en => generator2On_d,
generatorDelta => to_sfixed(generatorDelta_2_i, bH,bL),
kot_gen => kot_gen_2,
q_gen => q_gen_2
);
clk => clk_in,
clk_en => generator2On_d,
generatorDelta => to_sfixed(generatorDelta_2_i, bH,bL),
phase_sync => phase_sync_i,
phase_val => to_sfixed(phase_val_i, bH, bL),
kot_gen => kot_gen_2,
q_gen => q_gen_2
);
-- cordic_par_core_1 : cordic_par
-- port map (
......@@ -331,7 +349,12 @@ begin
if (rising_edge(clk_in)) then
generator1On_d <= generator1On;
generator2On_d <= generator2On;
generator2On_d <= generator2On;
if generator2On_dd = '0' and generator2On_d = '1' then
phase_sync_i <= '1';
else
phase_sync_i <= phase_sync;
end if;
if ( generator1On_d = '1' OR generator2On_d = '1' ) then
......@@ -350,7 +373,8 @@ begin
generatorDuty_1d <= generatorDuty_1;
generatorCustomSample_1d <= generatorCustomSample_1;
random_num_1_tmp <= signed(random_num_1);
generatorDelta_1_i <= '0' & generatorDelta_1(31 downto 1);
--utilize DSP block (multiply/add)
genSignal_1_tmp_d <= genSignal_1_tmp;
genSignal_1_tmp_dd <= genSignal_1_tmp_d;
......@@ -375,7 +399,6 @@ begin
--======================
if unsigned(generatorType_1d) = 0 then
generatorDelta_1_i <= '0' & generatorDelta_1(31 downto 1);
genSignal_1_tmp <= signed(generatorCustomSample_1d); -- read Custom Sample from RAM
---genSignal_tmp <= signed(awg_doutB(11 downto 0));
-- increment RAM address according to angle generator output
......@@ -395,7 +418,6 @@ begin
--======================
elsif unsigned(generatorType_1d) = 1 then
generatorDelta_1_i <= '0' & generatorDelta_1(31 downto 1);
-- generate phase
if q_gen_1(0) = '0' then
kot_gen_1_tmp <= std_logic_vector(signed(kot_gen_1(bH downto 0)));
......@@ -418,7 +440,6 @@ begin
--======================
elsif unsigned(generatorType_1d) = 2 then
generatorDelta_1_i <= '0' & generatorDelta_1(31 downto 1);
-- generate phase
if q_gen_1(0) = '0' then
kot_gen_1_tmp <= std_logic_vector(signed(kot_gen_1(bH downto 0)));
......@@ -441,15 +462,11 @@ begin
--======================
elsif unsigned(generatorType_1d) = 3 then
generatorDelta_1_i <= generatorDelta_1;
if q_gen_1 = "00" then
genSignal_1_tmp <= signed(kot_gen_1(bH downto bH-11));
elsif q_gen_1 = "01" then
genSignal_1_tmp <= to_signed(2047,12)-signed(kot_gen_1(bH downto bH-11));
elsif q_gen_1 = "10" then
genSignal_1_tmp <= -signed(kot_gen_1(bH downto bH-11));
else
genSignal_1_tmp <= to_signed(-2047,12)+signed(kot_gen_1(bH downto bH-11));
if q_gen_1 = "00" OR q_gen_1 = "10" then
genSignal_1_tmp <= to_signed(-2048,12)+signed(kot_gen_1(bH-1 downto bH-12));
--signed(kot_gen_2(bH downto bH-11));
elsif q_gen_1 = "01" OR q_gen_1 = "11" then
genSignal_1_tmp <= to_signed(2047,12)-signed(kot_gen_1(bH-1 downto bH-12));
end if;
enable_rand_1 <= '0';
......@@ -458,7 +475,6 @@ begin
--======================
elsif unsigned(generatorType_1d) = 4 then
generatorDelta_1_i <= '0' & generatorDelta_1(31 downto 1);
if q_gen_1(0) = '0' then
genSignal_1_tmp <= signed(kot_gen_1(bH downto bH-11));
else
......@@ -471,7 +487,6 @@ begin
--======================
elsif unsigned(generatorType_1d) = 5 then
generatorDelta_1_i <= '0' & generatorDelta_1(31 downto 1);
if q_gen_1(0) = '0' then
genSignal_1_tmp <= -signed(kot_gen_1(bH downto bH-11));
else
......@@ -484,11 +499,18 @@ begin
--======================
elsif unsigned(generatorType_1d) = 6 then
generatorDelta_1_i <= "00" & generatorDelta_1(31 downto 2);
if signed(kot_gen_1(bH downto bH-11)) < generatorDuty_1d then
genSignal_1_tmp <= to_signed(2047,12);
if q_gen_1(0) = '1' then
if signed(kot_gen_1(bH downto bH-11)) < 2*(to_signed(-1024,12)+generatorDuty_1d) then
genSignal_1_tmp <= to_signed(2047,12);
else
genSignal_1_tmp <= to_signed(-2047,12);
end if;
else
genSignal_1_tmp <= to_signed(-2047,12);
if signed(kot_gen_1(bH downto bH-11)) < 2*(generatorDuty_1d) then
genSignal_1_tmp <= to_signed(2047,12);
else
genSignal_1_tmp <= to_signed(-2047,12);
end if;
end if;
enable_rand_1 <= '0';
......@@ -496,10 +518,9 @@ begin
-- Delta
--======================
elsif unsigned(generatorType_1d) = 7 then
generatorDelta_1_i <= generatorDelta_1;
q_gen_1_d1 <= q_gen_1(1);
if q_gen_1_d1 = '1' and q_gen_1(1) = '0' then
elsif unsigned(generatorType_1d) = 7 then
q_gen_1_d1 <= q_gen_1(0);
if q_gen_1_d1 = '1' and q_gen_1(0) = '0' then
genSignal_1_tmp <= to_signed(2047,12);
else
genSignal_1_tmp <= to_signed(-2047,12);
......@@ -518,7 +539,6 @@ begin
--======================
elsif unsigned(generatorType_1d) = 9 then
generatorDelta_1_i <= generatorDelta_1;
enable_rand_1 <= '1';
genSignal_1_tmp <= random_num_1_tmp;
......@@ -532,7 +552,7 @@ begin
-- --connect generator #2 to cordic core
-- kot_gen <= kot_gen_2;
-- q_gen <= q_gen_2;
--registers inputs
generatorType_2d <= generatorType_2;
generatorVoltage_2d <= generatorVoltage_2;
......@@ -541,7 +561,9 @@ begin
generatorDuty_2d <= generatorDuty_2;
generatorCustomSample_2d <= generatorCustomSample_2;
random_num_2_tmp <= signed(random_num_2);
generatorDelta_2_i <= '0' & generatorDelta_2(31 downto 1);
phase_val_i <= phase_val & std_logic_vector(to_unsigned(0,abs(bL)));
--utilize DSP block (multiply/add)
genSignal_2_tmp_d <= genSignal_2_tmp;
genSignal_2_tmp_dd <= genSignal_2_tmp_d;
......@@ -558,7 +580,7 @@ begin
genSignal_2 <= genSignal_2_ii;
--Converting from Two's Complement to Offset Binary
--dac_data_2 <= std_logic_vector( genSignal_2_ii + to_signed(2048,12) ); --add Offset
dac_data_2 <= std_logic_vector( NOT(genSignal_2_ii(11)) & genSignal_2_ii(10 downto 0) ) ; --convert to offseet binary
dac_data_2 <= std_logic_vector( NOT(genSignal_2_ii(11)) & genSignal_2_ii(10 downto 0) ) ; --convert to offset binary
-- dac_data_2 <= dac_data_2_test;
--======================
......@@ -566,7 +588,6 @@ begin
--======================
if unsigned(generatorType_2d) = 0 then
generatorDelta_2_i <= '0' & generatorDelta_2(31 downto 1);
genSignal_2_tmp <= signed(generatorCustomSample_2d); -- read Custom Sample from RAM
---genSignal_tmp <= signed(awg_doutB(11 downto 0));
-- increment RAM address according to angle generator output
......@@ -586,7 +607,6 @@ begin
--======================
elsif unsigned(generatorType_2d) = 1 then
generatorDelta_2_i <= '0' & generatorDelta_2(31 downto 1);
-- generate phase
if q_gen_2(0) = '0' then
kot_gen_2_tmp <= std_logic_vector(signed(kot_gen_2(bH downto 0)));
......@@ -609,7 +629,6 @@ begin
--======================
elsif unsigned(generatorType_2d) = 2 then
generatorDelta_2_i <= '0' & generatorDelta_2(31 downto 1);
-- generate phase
if q_gen_2(0) = '0' then
kot_gen_2_tmp <= std_logic_vector(signed(kot_gen_2(bH downto 0)));
......@@ -632,24 +651,19 @@ begin
--======================
elsif unsigned(generatorType_2d) = 3 then
generatorDelta_2_i <= generatorDelta_2;
if q_gen_2 = "00" then
genSignal_2_tmp <= signed(kot_gen_2(bH downto bH-11));
elsif q_gen_2 = "01" then
genSignal_2_tmp <= to_signed(2047,12)-signed(kot_gen_2(bH downto bH-11));
elsif q_gen_2 = "10" then
genSignal_2_tmp <= -signed(kot_gen_2(bH downto bH-11));
else
genSignal_2_tmp <= to_signed(-2047,12)+signed(kot_gen_2(bH downto bH-11));
if q_gen_2 = "00" OR q_gen_2 = "10" then
genSignal_2_tmp <= to_signed(-2048,12)+signed(kot_gen_2(bH-1 downto bH-12));
--signed(kot_gen_2(bH downto bH-11));
elsif q_gen_2 = "01" OR q_gen_2 = "11" then
genSignal_2_tmp <= to_signed(2047,12)-signed(kot_gen_2(bH-1 downto bH-12));
end if;
enable_rand_2 <= '0';
enable_rand_2 <= '0';
--======================
-- Ramp Up
--======================
elsif unsigned(generatorType_2d) = 4 then
generatorDelta_2_i <= '0' & generatorDelta_2(31 downto 1);
if q_gen_2(0) = '0' then
genSignal_2_tmp <= signed(kot_gen_2(bH downto bH-11));
else
......@@ -662,7 +676,6 @@ begin
--======================
elsif unsigned(generatorType_2d) = 5 then
generatorDelta_2_i <= '0' & generatorDelta_2(31 downto 1);
if q_gen_2(0) = '0' then
genSignal_2_tmp <= -signed(kot_gen_2(bH downto bH-11));
else
......@@ -675,11 +688,18 @@ begin
--======================
elsif unsigned(generatorType_2d) = 6 then
generatorDelta_2_i <= "00" & generatorDelta_2(31 downto 2);
if signed(kot_gen_2(bH downto bH-11)) < generatorDuty_2d then
genSignal_2_tmp <= to_signed(2047,12);
if q_gen_2(0) = '1' then
if signed(kot_gen_2(bH downto bH-11)) < 2*(to_signed(-1024,12)+generatorDuty_2d) then
genSignal_2_tmp <= to_signed(2047,12);
else
genSignal_2_tmp <= to_signed(-2047,12);
end if;
else
genSignal_2_tmp <= to_signed(-2047,12);
if signed(kot_gen_2(bH downto bH-11)) < 2*(generatorDuty_2d) then
genSignal_2_tmp <= to_signed(2047,12);
else
genSignal_2_tmp <= to_signed(-2047,12);
end if;
end if;
enable_rand_2 <= '0';
......@@ -688,9 +708,8 @@ begin
--======================
elsif unsigned(generatorType_2d) = 7 then
generatorDelta_2_i <= generatorDelta_2;
q_gen_2_d1 <= q_gen_2(1);
if q_gen_2_d1 = '1' and q_gen_2(1) = '0' then
q_gen_2_d1 <= q_gen_2(0);
if q_gen_2_d1 = '1' and q_gen_2(0) = '0' then
genSignal_2_tmp <= to_signed(2047,12);
else
genSignal_2_tmp <= to_signed(-2047,12);
......@@ -710,7 +729,6 @@ begin
--======================
elsif unsigned(generatorType_2d) = 9 then
generatorDelta_2_i <= generatorDelta_2;
genSignal_2_tmp <= random_num_2_tmp;
enable_rand_2 <= '1';
......
......@@ -31,16 +31,18 @@ architecture Behavioral of awg_core_tb is
component awg_core is
generic (
bH : integer := 11; -- angle input precision high index
bL : integer := -20 -- angle input precision low index
bH : integer := 14; -- angle input precision high index
bL : integer := -17 -- angle input precision low index