Commit 6f044bc0 authored by Dejan Priversek's avatar Dejan Priversek
Browse files

immediate trigger fix

parent 583ff90a
......@@ -542,3 +542,82 @@ set_property LOC SLICE_X8Y7 [get_cells lut_delay_inst/FDRE0_inst_31]
#connect_debug_port dbg_hub/clk [get_nets ifclk]
#debug immediate trigger
#create_debug_core u_ila_0 ila
#set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
#set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
#set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
#set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
#set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
#set_property C_INPUT_PIPE_STAGES 2 [get_debug_cores u_ila_0]
#set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
#set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
#set_property port_width 1 [get_debug_ports u_ila_0/clk]
#connect_debug_port u_ila_0/clk [get_nets [list RAM_DDR3_inst/RAM/u_mig_ddr3/u_mig_ddr3_mig/u_ddr3_infrastructure/CLK]]
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
#set_property port_width 9 [get_debug_ports u_ila_0/probe0]
#connect_debug_port u_ila_0/probe0 [get_nets [list {slwr_assert_cnt[0]} {slwr_assert_cnt[1]} {slwr_assert_cnt[2]} {slwr_assert_cnt[3]} {slwr_assert_cnt[4]} {slwr_assert_cnt[5]} {slwr_assert_cnt[6]} {slwr_assert_cnt[7]} {slwr_assert_cnt[8]}]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
#set_property port_width 3 [get_debug_ports u_ila_0/probe1]
#connect_debug_port u_ila_0/probe1 [get_nets [list {slrd_rdy_cnt[0]} {slrd_rdy_cnt[1]} {slrd_rdy_cnt[2]}]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
#set_property port_width 10 [get_debug_ports u_ila_0/probe2]
#connect_debug_port u_ila_0/probe2 [get_nets [list {slrd_cnt[0]} {slrd_cnt[1]} {slrd_cnt[2]} {slrd_cnt[3]} {slrd_cnt[4]} {slrd_cnt[5]} {slrd_cnt[6]} {slrd_cnt[7]} {slrd_cnt[8]} {slrd_cnt[9]}]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
#set_property port_width 27 [get_debug_ports u_ila_0/probe3]
#connect_debug_port u_ila_0/probe3 [get_nets [list {send_sample_cnt[0]} {send_sample_cnt[1]} {send_sample_cnt[2]} {send_sample_cnt[3]} {send_sample_cnt[4]} {send_sample_cnt[5]} {send_sample_cnt[6]} {send_sample_cnt[7]} {send_sample_cnt[8]} {send_sample_cnt[9]} {send_sample_cnt[10]} {send_sample_cnt[11]} {send_sample_cnt[12]} {send_sample_cnt[13]} {send_sample_cnt[14]} {send_sample_cnt[15]} {send_sample_cnt[16]} {send_sample_cnt[17]} {send_sample_cnt[18]} {send_sample_cnt[19]} {send_sample_cnt[20]} {send_sample_cnt[21]} {send_sample_cnt[22]} {send_sample_cnt[23]} {send_sample_cnt[24]} {send_sample_cnt[25]} {send_sample_cnt[26]}]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
#set_property port_width 2 [get_debug_ports u_ila_0/probe4]
#connect_debug_port u_ila_0/probe4 [get_nets [list {faddr_i[0]} {faddr_i[1]}]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
#set_property port_width 3 [get_debug_ports u_ila_0/probe5]
#connect_debug_port u_ila_0/probe5 [get_nets [list {DebugMState[0]} {DebugMState[1]} {DebugMState[2]}]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
#set_property port_width 1 [get_debug_ports u_ila_0/probe6]
#connect_debug_port u_ila_0/probe6 [get_nets [list DataOutEnable]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
#set_property port_width 1 [get_debug_ports u_ila_0/probe7]
#connect_debug_port u_ila_0/probe7 [get_nets [list DataOutValid]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
#set_property port_width 1 [get_debug_ports u_ila_0/probe8]
#connect_debug_port u_ila_0/probe8 [get_nets [list flaga_d]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
#set_property port_width 1 [get_debug_ports u_ila_0/probe9]
#connect_debug_port u_ila_0/probe9 [get_nets [list flagb_d]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
#set_property port_width 1 [get_debug_ports u_ila_0/probe10]
#connect_debug_port u_ila_0/probe10 [get_nets [list flagd_d]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
#set_property port_width 1 [get_debug_ports u_ila_0/probe11]
#connect_debug_port u_ila_0/probe11 [get_nets [list newFrameRequestRevcd]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
#set_property port_width 1 [get_debug_ports u_ila_0/probe12]
#connect_debug_port u_ila_0/probe12 [get_nets [list slrd_i]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
#set_property port_width 1 [get_debug_ports u_ila_0/probe13]
#connect_debug_port u_ila_0/probe13 [get_nets [list slwr_assert]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
#set_property port_width 1 [get_debug_ports u_ila_0/probe14]
#connect_debug_port u_ila_0/probe14 [get_nets [list slwr_i]]
#create_debug_port u_ila_0 probe
#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
#set_property port_width 1 [get_debug_ports u_ila_0/probe15]
#connect_debug_port u_ila_0/probe15 [get_nets [list wea_awg]]
#set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
#connect_debug_port dbg_hub/clk [get_nets ifclk]
......@@ -1713,7 +1713,7 @@ begin
saved_sample_cnt <= to_integer(unsigned(pre_trigger_d));
-- if immediate trigger (roll mode)
if trigger_mode_d = "11" and pre_trigger_d = 0 then
GetSampleState <= ADC_E;
GetSampleState <= ADC_C;
triggered_led <= '1'; -- signal IS TRIGGERED indicator
-- if not immediate trigger, goto "WAIT FOR TRIGGER ARMED"
else
......
......@@ -104,7 +104,7 @@ begin
else
kot_gen_tmp <= '0' & next_angle(bH-1 downto 0); -- angle output (0 to 2047)
kot_gen_tmp <= '0' & next_angle(bH-1 downto 0); -- angle output (0 to 16383)
kot_gen <= kot_gen_tmp;
q_gen_tmp <= std_logic_vector(to_unsigned(quadrant,2));
q_gen <= q_gen_tmp;
......@@ -121,7 +121,7 @@ begin
curr_angle <= resize( arg => curr_angle + generatorDelta_dd,
left_index => bH,
right_index => bL,
overflow_style => fixed_wrap); -- start from 0 if overflow
overflow_style => fixed_wrap); -- discards the overflow bit
next_angle <= curr_angle;
end if; -- phase_sync
......
......@@ -97,7 +97,7 @@ architecture Behavioral of awg_core_tb is
--AWG2
signal genSignal_2 : signed (11 downto 0);
signal ram_addrb_awg_2 : STD_LOGIC_VECTOR (14 downto 0);
signal generatorType_2 : STD_LOGIC_VECTOR (3 downto 0) := std_logic_vector(to_unsigned(0,4));
signal generatorType_2 : STD_LOGIC_VECTOR (3 downto 0) := std_logic_vector(to_unsigned(1,4));
signal generatorVoltage_2 : sfixed(0 downto -11):="011111111111";
signal generatorOffset_2 : SIGNED (11 downto 0):="000000000000";
signal generatorDuty_2 : signed(11 downto 0):="000000000000";
......@@ -182,8 +182,8 @@ begin
wait until rising_edge(clk);
generator1On <= '1';
generatorDelta_1 <= std_logic_vector(to_unsigned(100000000,bH-bL+1));
generatorDelta_2 <= std_logic_vector(to_unsigned(100000000,bH-bL+1));
generatorDelta_1 <= "01010000000000000000000000000000";
generatorDelta_2 <= "01010000000000000000000000000000";
generatorType_1 <= std_logic_vector(to_unsigned(3,4));
generatorType_2 <= std_logic_vector(to_unsigned(3,4));
generatorDuty_1 <= "000000000000";
......
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