Commit 15a54dd5 authored by Dejan Priversek's avatar Dejan Priversek
Browse files

replace DDR3 read fifo with xilinx fifo generator, fix DDR3 write fifo reads,...

replace DDR3 read fifo with xilinx fifo generator, fix DDR3 write fifo reads, update vivado project generation script
parent bdfdfc96
This diff is collapsed.
......@@ -22,14 +22,3 @@ set_property CFGBVS GND [current_design]
set_property CONFIG_MODE S_SERIAL [current_design]
set_property BITSTREAM.CONFIG.PERSIST NO [current_design]
set_property BITSTREAM.STARTUP.STARTUPCLK CCLK [current_design]
This diff is collapsed.
......@@ -82,9 +82,10 @@ set_max_delay -datapath_only -from [get_pins clearflags_reg/C] -to [get_pins cle
set_max_delay -datapath_only -from [get_pins sig_out_enable_reg/C] -to [get_pins sig_out_enable_d_reg/D] 2.000
set_max_delay -datapath_only -from [get_pins requestFrame_reg/C] -to [get_pins requestFrame_d_reg/D] 2.000
set_max_delay -datapath_only -from [get_pins RAM_DDR3_inst/PreTrigSavingCntRecvd_reg/C] -to [get_pins RAM_DDR3_inst/PreTrigSavingCntRecvd_d_reg/D] 2.000
set_max_delay -datapath_only -from [get_pins {RAM_DDR3_inst/PreTrigSavingCnt_reg[*]/C}] -to [get_pins {RAM_DDR3_inst/PreTrigSavingCnt_d_reg[*]/D}] 2.000
set_max_delay -datapath_only -from [get_pins RAM_DDR3_inst/ram_rdy_i_reg/C] -to [get_pins RAM_DDR3_inst/ram_rdy_reg/D] 2.000
set_max_delay -datapath_only -from [get_pins {pre_trigger_d_reg[*]/C}] -to [get_pins {RAM_DDR3_inst/RAM/wr_pretriglen_reg[*]/D}] 2.000
#DDR3 controller
# write FIFO reset
# clk_adc -> clk_fx3
......@@ -133,3 +134,4 @@ set_max_delay -datapath_only -from [get_pins {DebugADCState_reg[*]/C}] -to [get_
......@@ -101,21 +101,22 @@ architecture Behavioral of RAM_DDR3 is
--Read FIFO:
component fifo_128_to_32
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteEn : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (127 downto 0);
ReadEn : in STD_LOGIC;
DataOut : out STD_LOGIC_VECTOR (31 downto 0);
DataOutValid : out STD_LOGIC;
Empty : out STD_LOGIC;
AlmostEmpty : out STD_LOGIC;
Full : out STD_LOGIC;
AlmostFull : out STD_LOGIC
);
end component;
COMPONENT fifo_gen_0
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
--DDR3 interface top level:
......@@ -296,6 +297,7 @@ attribute mark_debug of frd_Full : signal is true;
attribute mark_debug of frd_Empty : signal is true;
attribute mark_debug of ui_rd_data_available : signal is true;
attribute mark_debug of frd_DataOut : signal is true;
attribute mark_debug of fwr_DataOut : signal is true;
attribute keep of ui_frameStart: signal is true;
attribute mark_debug of ui_frameStart : signal is true;
......@@ -331,21 +333,23 @@ RAM_WRITE_FIFO: fifo_32_to_128 PORT MAP (
AlmostEmpty => fwr_AlmostEmpty,
AlmostFull => fwr_AlmostFull
);
RAM_READ_FIFO: fifo_128_to_32 PORT MAP (
CLK => ui_clk_i,
RST => rst,
DataIn => frd_DataIn,
WriteEn => frd_WriteEn,
ReadEn => frd_ReadEn,
DataOut => frd_DataOut,
DataOutValid => frd_DataOutValid,
Full => frd_Full,
Empty => frd_Empty,
AlmostEmpty => frd_AlmostEmpty,
AlmostFull => frd_AlmostFull
);
RAM_READ_FIFO: fifo_gen_0
PORT MAP (
clk => ui_clk_i,
srst => rst,
din => frd_DataIn,
wr_en => frd_WriteEn,
rd_en => frd_ReadEn,
dout => frd_DataOut,
full => frd_Full,
almost_full => open,
empty => frd_Empty,
almost_empty => frd_AlmostEmpty,
valid => frd_DataOutValid,
prog_full => frd_AlmostFull
);
RAM: ddr3_simple_ui PORT MAP (
-- DDR3 simple user interface
sys_clk_i => sys_clk_i,
......@@ -522,7 +526,7 @@ begin
if frd_AlmostFull_d = '1' then
frd_ReadEn <= '1';
-- if read fifo is empty, stop reading data from it
elsif frd_Empty = '1' then
elsif frd_AlmostEmpty = '1' then
frd_ReadEn <= '0';
-- if all samples have been read out of RAM
elsif frd_data_cnt >= unsigned(FrameSize)/4 then
......@@ -533,6 +537,7 @@ begin
-- read is not requested and complete frame was transfered
-- but read fifo is still not empty
-- this can happen if more samples were saved in RAM than framesize
-- or frame rearing was aborted before reading full frame
--if DataOutEnable = '0' and ReadingFrame = '0' and frd_Empty = '0' then
if ReadingFrame = '0' and frd_data_cnt >= unsigned(FrameSize)/4 and frd_Empty = '0'then
-- assert read enable to read redundant samples from read fifo
......
......@@ -390,7 +390,7 @@ architecture rtl of fpga is
o_data : out std_logic_vector(9 downto 0));
end component;
signal clk_adc_dclk : std_logic;
signal clk_adc_dclk : std_logic;
signal clk_adc_p_delayed : std_logic;
signal clk_adc_n_delayed : std_logic;
......@@ -1039,10 +1039,6 @@ port map (
rst => clearflags,
FrameSize => framesize_dd,
DataIn => DDR3DataIn,
--DataIn => std_logic_vector(to_unsigned(saved_sample_cnt_d,32)), --* debug!
-- DataIn => std_logic_vector(DataInTest (9 downto 0))
-- & std_logic_vector(DataInTest (9 downto 0))
-- & std_logic_vector(DataInTest(11 downto 0)),
PreTrigSaving => PreTrigSaving,
PreTrigWriteEn => PreTrigWriteEn_d,
PreTrigLen => std_logic_vector(pre_trigger_d),
......@@ -1361,6 +1357,10 @@ pktend <= '1'; -- TODO:
--LED_i(1) <= not(dac_pll_locked); -- debug led
DDR3DataIn <= std_logic_vector(dataAd) & std_logic_vector(dataBd) & dataDd(11 downto 0);
--DDR3DataIn <= std_logic_vector(to_unsigned(saved_sample_cnt_d,32)); --* debug!
--DDR3DataIn <= std_logic_vector(DataInTest (9 downto 0))
-- & std_logic_vector(DataInTest (9 downto 0))
-- & std_logic_vector(DataInTest(11 downto 0));
ADC_interface_rising: process(clk_adc_dclk)
......
......@@ -27,27 +27,43 @@ ENTITY fifo_128_to_32_tb IS
END fifo_128_to_32_tb;
ARCHITECTURE behavior OF fifo_128_to_32_tb IS
COMPONENT fifo_gen_0
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Component Declaration for the Unit Under Test (UUT)
component fifo_128_to_32
Generic (
constant DATA_IN_WIDTH : positive := 128;
constant FIFO_DEPTH : positive := 512
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteEn : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (DATA_IN_WIDTH - 1 downto 0);
ReadEn : in STD_LOGIC;
DataOut : out STD_LOGIC_VECTOR (DATA_IN_WIDTH/4 - 1 downto 0);
DataOutValid : out std_logic;
Empty : out STD_LOGIC;
AlmostEmpty : out STD_LOGIC;
Full : out STD_LOGIC;
AlmostFull : out STD_LOGIC
);
end component;
-- component fifo_128_to_32
-- Generic (
-- constant DATA_IN_WIDTH : positive := 128;
-- constant FIFO_DEPTH : positive := 512
-- );
-- port (
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- WriteEn : in STD_LOGIC;
-- DataIn : in STD_LOGIC_VECTOR (DATA_IN_WIDTH - 1 downto 0);
-- ReadEn : in STD_LOGIC;
-- DataOut : out STD_LOGIC_VECTOR (DATA_IN_WIDTH/4 - 1 downto 0);
-- DataOutValid : out std_logic;
-- Empty : out STD_LOGIC;
-- AlmostEmpty : out STD_LOGIC;
-- Full : out STD_LOGIC;
-- AlmostFull : out STD_LOGIC
-- );
-- end component;
constant DATA_IN_WIDTH : integer := 128;
constant FIFO_DEPTH : integer := 512;
......@@ -81,21 +97,36 @@ ARCHITECTURE behavior OF fifo_128_to_32_tb IS
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fifo_128_to_32
uut: fifo_gen_0
PORT MAP (
CLK => CLK,
RST => RST,
DataIn => DataIn,
WriteEn => WriteEn,
ReadEn => ReadEn,
DataOut => DataOut,
DataOutValid => DataOutValid,
Full => Full,
Empty => Empty,
AlmostEmpty => AlmostEmpty,
AlmostFull => AlmostFull
clk => CLK,
srst => RST,
din => DataIn,
wr_en => WriteEn,
rd_en => ReadEn,
dout => DataOut,
full => Full,
almost_full => AlmostFull,
empty => Empty,
almost_empty => AlmostEmpty,
valid => DataOutValid
);
-- uut: fifo_128_to_32
-- PORT MAP (
-- CLK => CLK,
-- RST => RST,
-- DataIn => DataIn,
-- WriteEn => WriteEn,
-- ReadEn => ReadEn,
-- DataOut => DataOut,
-- DataOutValid => DataOutValid,
-- Full => Full,
-- Empty => Empty,
-- AlmostEmpty => AlmostEmpty,
-- AlmostFull => AlmostFull
-- );
-- Clock process definitions
CLK_process :process
begin
......@@ -152,7 +183,7 @@ BEGIN
-- or AlmostEmpty rising edge (then start writing to fifo)
elsif AlmostEmpty_d = '0' and AlmostEmpty = '1' then
WriteEn <= '1';
DataIn <= X"000000DD000000010000000200000003";
--DataIn <= X"000000DD000000010000000200000003";
end if;
if writing_frame = '1' then
if wr_skip_cnt = 23 then
......@@ -187,7 +218,7 @@ BEGIN
for i in 0 to 150 loop
wait until rising_edge(clk);
flagd <= '0';
for i in 0 to 56 loop
for i in 0 to 12095 loop
wait until rising_edge(clk);
end loop;
flagd <= '1';
......@@ -214,7 +245,7 @@ BEGIN
for i in 1 to 70 loop
for i in 1 to 1024 loop
wait until rising_edge(clk);
if flagd = '1' then
if flagd = '1' and AlmostEmpty = '0' then
ReadEn <= '1';
else
ReadEn <= '0';
......
......@@ -241,7 +241,7 @@ fifo_proc: process (clk_wr)
when 1 =>
in_pkt_sel <= 2;
DataIn_1(31 downto 0) <= DataIn;
WriteEn_1 <= '1';
WriteEn_1 <= '0';
WriteEn_2 <= '0';
when 2 =>
in_pkt_sel <= 3;
......@@ -251,7 +251,7 @@ fifo_proc: process (clk_wr)
when 3 =>
in_pkt_sel <= 0;
DataIn_2(31 downto 0) <= DataIn;
WriteEn_1 <= '0';
WriteEn_1 <= '1';
WriteEn_2 <= '1';
when others =>
null;
......
......@@ -21,16 +21,19 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
......@@ -38,9 +41,13 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue>
......@@ -59,6 +66,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue>
......@@ -72,6 +80,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
......@@ -635,7 +644,8 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a35t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ftg256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
......@@ -646,17 +656,35 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.3_AR71898</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
......
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