[qblox backend] Reset NCO clock phase on every measurement (#296, QAE-150)
Explanation of changes
As described in #296 (closed) it is desirable to have the phase of the measurement clock to be set to zero at the start of every measurement. A reset_clock_phase
parameter is introduced to the device_config and can be set to True/False directly through a BasicTransmonElement
.
For example:
q0.measure.reset_clock_phase(True)
device_cgf = quantum_device.generate_device_config()
schedule = Schedule(f"Test schedule")
schedule.add(X90("q0"))
schedule.add(Measure("q0"))
compiled_schedule = qcompile(schedule, device_cgf, hardware_cfg)
generates the following QASM code (on qblox devices) for seq0
on the qrm
wait_sync 4
upd_param 4
set_mrk 15 # set markers to 15
wait 4 # latency correction of 4 + 0 ns
move 1,R0 # iterator for loop with label start
start:
reset_ph
upd_param 4
wait 20 # auto generated wait (20 ns)
reset_ph
set_awg_gain 32,0 # setting gain for Measure q0
play 0,1,4 # play Measure q0 (160 ns)
wait 116 # auto generated wait (116 ns)
acquire 0,0,4
wait 296 # auto generated wait (296 ns)
loop R0,@start
set_mrk 0 # set markers to 0
upd_param 4
stop
while setting q0.measure.reset_clock_phase(False)
will generate
wait_sync 4
upd_param 4
set_mrk 15 # set markers to 15
wait 4 # latency correction of 4 + 0 ns
move 1,R0 # iterator for loop with label start
start:
reset_ph
upd_param 4
wait 20 # auto generated wait (20 ns)
set_awg_gain 32,0 # setting gain for Measure q0
play 0,1,4 # play Measure q0 (160 ns)
wait 116 # auto generated wait (116 ns)
acquire 0,0,4
wait 296 # auto generated wait (296 ns)
loop R0,@start
set_mrk 0 # set markers to 0
upd_param 4
stop
Note that q0.measure.reset_clock_phase(True)
is the default behavior. Also, note that currently the resetting of the NCO clock phase is only supported by the qblox backend.
Under the hood this is achieved by implementing a new class operations.pulse_library.ResetClockPhase
which is added as a pulse right before a measurement pulse during compilation if q0.measure.reset_clock_phase
is set to True
. Later on this pulse is translated to Q1ASM code via backends.qblox.operation_handling.virtual.NcoResetClockPhaseStrategy
, which simply adds a line reset_ph
to the existing q1asm program.
Note
Real signals can be output on odd outputs in real mode but lead to a 90-degree phase shift. The current fix does not take that into account, but the clock phase is constant across measurements, so not necessarily a problem.
Closes #296 (closed)
Merge checklist
See also merge request guidelines
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Merge request has been reviewed and approved by a project maintainer. -
Merge request contains a clear description of the proposed changes and the issue it addresses. -
Merge request made onto appropriate branch (main for most MRs). -
New code is fully tested. -
New code is documented and docstrings use numpydoc format. -
CHANGELOG.rst
andAUTHORS.rst
have been updated (when applicable). -
CI pipelines pass -
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passes (gitlab-ci), - test suite passes (gitlab-ci),
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-
windows tests pass (manually triggered by maintainers before merging).
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