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The special cache check done when skiboot is compiled with DEBUG is incompatible with Automatic Context Save and Restore. Random data is written in the NVP to check that cache updates are correct but this can lead to a checkstop raised by the XIVE interrupt controller. When the NVP Valid (0) bit, the hardware controlled H (7) bit, and the Checked Out bit (45) are all ones at the same time, the HW thinks that the NVP entry is checked out by a thread and does not allow the cache write to occur. Make sure that the valid bit is not set on the NVP. Signed-off-by:
Cédric Le Goater <clg@kaod.org> Signed-off-by:
Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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HW has some reserved fields which break the comparison when checking END cache updates. Signed-off-by:
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We only support the XIVE interface. Signed-off-by:
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An hw issue was found on P10 (HW560152) where a page-level TCE kill can be dropped if there are enough TCE kill requests already being processed. The net effect is that data integrity is not guaranteed. The circumvention is to stay away from page-level kills and escalate those to PE kills. Which hurts performance. It also affects P9. Signed-off-by:
Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by:
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hegdevasant authored
Move to qemu version powernv-6.1. Signed-off-by: -
hegdevasant authored
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Make it a bit easier to boot large kernels by printing more info when the kernel is too big, so the user has some idea how much they need to adjust PAYLOAD_ADDR by. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au> Signed-off-by:
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Update the table of platforms to make it clear which Power9 CPU each uses, currently they all use Power9N. Signed-off-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
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npu3 was only used on the Swift platform to add support for GPUs (nvlink). The Swift platform has never left the lab and support for GPUs on it is pretty much dead. So let's remove it. The patch removes all related code. Device tree entries are no longer created and in the very unlikely case that someone is still trying to boot it, the linux nvlink discovery code should be quiet. Tested by booting on Swift with no GPU. Signed-off-by:
Reza Arbab <arbab@linux.ibm.com> Signed-off-by:
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There were a few instances in `get_hash_to_verify` where NULL is returned before unallocating the md context. This commit ensures that this memory is properly freed before returning. Signed-off-by:
Nick Child <nick.child@ibm.com> Signed-off-by:
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Update PVR and mambo f000f bits: - Set POWER10 to DD2.0 Update SIM_CTRL and SIM_CTRL1 bits: - Set the LPAR-per-core mode bit. This is required for SMT KVM to work. - Set ARC0/ARC1 bits which enable atomic RC update interrupts (not hardware updates), which matches implementation. - Enable DEXCR, HAIL, ROP, BHRB disable, block BHRB writes in PR=0, and RFC02628 on POWER10. Signed-off-by:
Nicholas Piggin <npiggin@gmail.com> Signed-off-by:
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Update SIM_CTRL1 bits to set ARC0/1, which disables atomic RC updates in hardware which matches implementation. Comment some remaining quirks with the P9 configuration. Signed-off-by:
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If the SMT configuration is not 8, set small-core mode in SIM_CTRL1 and PVR registers. Also allow only 1, 2, 4, or 8 threads, and only allow 1 and 2 threads if there is only one processor configured. This helps avoid strange crashes due to thread/core enumeration problems with unexpected threads per core. Signed-off-by:
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This patch removes the following properties from PHB entries in the device tree on P10, since there's no CAPP any more and the properties no longer make sense: ibm,phb-indications ibm,capp-timebase-sync ibm,capi-flags It has no effect on linux: some were already ignored and others won't even be read since the cxl driver (the only consumer) already fails early on P10. Signed-off-by:
Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by:
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Skiboot is using r16 as a fixed register containing this CPU pointer, but we can be called back into from hostboot via the host services interface, where r16 may have been set by hostboot. Switch this back to skiboot's CPU pointer before running host services handlers, and then restore it to the hostboot value before returning. Fixes: 11ce9612 ("move the __this_cpu register to r16, reserve r13-r15") Reported-by:
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On P10, get_ics_phandle() calls xive2_get_phandle() directly. This results in a NULL dereference on mambo when xive2 is not set up. This was caught with the virtual memory boot patch on P10 mambo. Signed-off-by:
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Calling cpu_relax resets the SMT priority to medium, causing the idle loop not to run with lowest priority. Just use barrier() instead, this saves about 3 seconds on a SMT4 systemsim (mambo) boot. Signed-off-by:
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If cpu_relax() is called when not at medium SMT priority, it will lose the prior priority and return at medium. Add a debug check to catch this, which would have flagged the previous bug. Signed-off-by:
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Fixes: 891ed8df ("Initial POWER10 enablement") Signed-off-by:
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This significantly simplifies the SLW code. HILE is now always supported. Reviewed-by:
Stewart Smith <stewart@flamingspork.com> Signed-off-by:
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Convert phb3 dt construction and in-memory hardware tables to use explicit endian conversions. Signed-off-by:
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Fix endian for the 4-byte LPC copy similarly to other flash drivers. This allows flash to be detected on POWER8 AST BMC systems with a LE skiboot. Fix incorrect comments in those other drivers while we're here. Signed-off-by:
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This patch enables Skiboot to initialize and Linux to boot to user space on the AWAN core and chip models. We need the distinction between core and chip models because the core models do not have an XSCOM unit, CHIPTOD, nor RNG. The chip model does have them and they work. So, add a device_type property to the awan node to distinguish core from chip. Sample DTS are provided for the core and chip models in external/awan. Just like Mambo, we need to return in slw_init before trying to initialize SLW. Without an XSCOM unit in the device tree for the core model, the SLW code path eventually fails an assert due to lack of chips. This commit defines a QUIRK_AWAN where previously Mambo used QUIRK_MAMBO_CALLOUTS so now Mambo and AWAN core both work. Also, fix up chip quirks so the core model and chip model boot and initialize the appropriate units. Disable sreset and power management in a couple spots because the chip model does not support stop with EC=1 and enter_p9_pm_state spins in the branch-to-self after stop. Provide an external/awan/README.md with a high-level view of booting in the environment. Signed-off-by:
Ryan Grimm <grimm@linux.ibm.com> Signed-off-by:
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Move the OPAL entry points for npu2 opencapi to the common opal NPU file. This prepares us to add same entries for PAU opencapi in this common file. No functional change. Signed-off-by:
Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by:
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OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable PHYs, Datalink Layer Logic and Transaction Layer Logic to be included. The PHYs are the physical connection to the OCAPI interconnect. The Datalink Layer provides link training. The Transaction Layer executes the cache coherent and data movement commands on the P10 chip. The PAU provides the Transaction Layer functionality for the OCAPI link(s) on the P10 chip. The P10 PAU supports two OCAPI links. Six accelerator units PAUs are instantiated on the P10 chip for a total of twelve OCAPI links. This patch adds PAU opencapi structure for supporting OpenCapi5. hw/pau.c file contains main of PAU management functions. Signed-off-by:
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Update the platform_ocapi structure to store Rainier platform-specific values for detecting and resetting OpenCAPI devices via the module I2C (PCA9553) The unique number I2C bus ID associated to each OpenCapi device is get from the I2C port and engine. (De)Assert a reset and detect an OpenCapi device is available through the I2C bus id and address. Signed-off-by:
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Configure early PAU Global MMIO BAR registers to allow PAU MMIO register accesses. This is done for each PAU. Enable the Powerbus interface is mandatory for MMIO accesses. For each OpenCAPI device, configure the bar registers to access to the AFU MMIO and to the AFU Config Addr/Data registers. AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K (= 0x50000) Signed-off-by:
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Implement the necessary operations for the OpenCAPI PHB type and inform the device-tree properties associated. The OpenCapi PCI config Addr/Data registers are reachable through the Generation-ID Registers MMIO BARS. The Config Address and Data registers are located at the following offsets from the AFU Config BAR plus 320 KB. • Config Address for Brick 0 – Offset 0 • Config Data for Brick 0 – Offsets: ◦ 128 – 4-byte config register • Config Address for Brick 1 – Offset 256 • Config Data for Brick 1 – Offsets: ◦ 384 – 4-byte config register Signed-off-by:
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Enable OpenCAPI mode for each brick which are connected to be used in this mode. This is be done through 7 steps as described in the P10 OCAPI 5.0 Processing Unit Workbook document, section: 17.1.3.1 Enabling OpenCAPI. The following sequences must be performed: 1. Set Transport MUX controls to select OpenCAPI 2. Enable Clocks in XSL 3. Enable Clocks in MISC 4. Set NPCQ configuration 5. Enable XSL-XTS Interfaces 6. Enable State-machine allocation Enabling the NTL/GENID BARS allows to access to the MMIO registers. Signed-off-by:
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Next main part of the hypervisor PAU initialization. The P10 PAU supports two OpenCAPI links. The PAU provides various configuration selections for both of the OCAPI Link Transaction Layer functions (OTLs). These include a link enable, behavior controls, debug modes, and virtual channel credits to send to the AFU. The OTL Configuration 0, OTL Configuration 1, OTL Configuration 2, and TLX Credit Configuration registers are used to control these functions. This patch completes the PAU configuration following the sections 17.1.3.4 to 17.1.3.10.2 of the workbook document. Signed-off-by:
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The default action for the errors (unexpected errors on the opencapi link) reported in the PAU FIR2 registe is mostly set to system checkstop. This patch changes the default action of those errors so that the PAU will raise an interrupt instead. Interrupt information are logged so that the error can be debugged and linux can catch the event. Signed-off-by:
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Add more PHB interfaces: - to control pci error type in case of freeze. - add the addresses of the registers needed by the OS to handle translation failures. - to detect the fence state of a specific brick - to configure BDF (Bus Device Function) and PE (Partitionable Endpoint) for context identification. Signed-off-by:
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This patch add a new function to dump PAU registers when a HMI has been raised and an OpenCAPI link has been hit by an error. For each register, the scom address and the register value are printed. The hmi.c has been redesigned in order to support the new PHB/PCIEX type (PAU OpenCapi). Now, the *npu* functions support NPU and PAU units of P8, P9 and P10 chips. Signed-off-by:
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Follow the Procedure IO_INIT_RESET_PON as described in the P10 OPHY workbook document to reset and initialize the PHY lanes. The memory mapped SRAM (64 bit aligned) has to be used to configure the PHY, which is reachable the linked registers: address and data. The different links can be configured at the same time, that implies using a global lock to avoid conflicts. Authored-by:
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Add elementary functions to handle a phb complete, fundamental and hot resets. For the time being, specific creset and hreset are not supported. A complete fundamental reset is based on the following steps, in this order: - Place all bricks into Fence state - Disable BARs - Reset ODL to Power-on Values - Set the i2c reset pin in output mode - Initialize PHY Lanes - Deassert ODL reset - Clear the the i2c reset pin - Unfence bricks - Enable BARs - Enable ODL training mode Link training is also set up. Signed-off-by:
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Update the content of three current OPAL API calls to support PAU. - OPAL_NPU_SPA_SETUP The Shared Process Area (SPA) is a table containing one entry (a "Process Element") per memory context which can be accessed by the OpenCAPI device. - OPAL_NPU_SPA_CLEAR_CACHE The PAU keeps a cache of recently accessed memory contexts. When a Process Element is removed from the SPA, the cache for the link must be cleared. - OPAL_NPU_TL_SET The Transaction Layer specification defines several templates for messages to be exchanged on the link. During link setup, the host and device must negotiate what templates are supported on both sides and at what rates those messages can be sent. Signed-off-by: -
The remaining translation mode: OpenCAPI 5.0 with TLBI/SLBI Snooping, is not used due to performance problems caused by the mismatch between the ERAT and Bloom Filter sizes. When the Address Translation Mode requires TLB and SLB Invalidate operations to be initiated using MMIO registers, a set of registers like the following is used: • XTS MMIO ATSD0 LPARID register • XTS MMIO ATSD0 AVA register • XTS MMIO ATSD0 launch register, write access initiates a shoot down • XTS MMIO ATSD0 status register Signed-off-by:
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Lowest Point of Coherency (LPC) memory allows the host to access memory on an OpenCAPI device. When the P10 chip accesses memory addresses on the AFU, the Real Address on the PowerBus must hit a BAR in the PAU such as GPU-Memory BAR. The BAR defines the range of Real Addresses that represent AFU memory. The two existing OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE are used to manage the AFU momory. Signed-off-by:
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This patch fixes errors seen when linux looks for the interrupt to use for a device LSI: pci X:Y:Z of_irq_parse_pci: failed with rc=-22 The of/irq parsing code requires those new properties to be able to map the interrupt specifier correctly. It was not needed before comitting cd12ea6d ("interrupts: Do not advertise XICS support on P10"), because the LSI mapping code was defaulting to the XICS interrupt controller node, which is now removed (and had those properties). Fixes: cd12ea6d ("interrupts: Do not advertise XICS support on P10") Signed-off-by: -
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hegdevasant authored
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hegdevasant authored
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All PHB5 error registers read when getting the PHB diagnostics data have the exact same definitions as on PHB4, so we don't need any new type. OPAL_PHB_ERROR_DATA_TYPE_PHB5 is not used in skiboot. It's never been imported on linux, so it is safe to remove the symbol. Signed-off-by:
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hegdevasant authored
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