target/riscv: mstatus.MPV and mstatus.GVA (mstatush on RV32) are read-only, so MRET cannot enter VS/VU-mode
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## Host environment
- Operating system:
AlmaLinux 9.7
- OS/kernel version:
- Linux 5.14.0-611.45.1.el9_7.x86_64
- Architecture:
x86
- QEMU flavor:
- qemu-system-riscv64
- QEMU version:
11.1.1 (also tested on master 5dfdb16ffa)
- QEMU command line:
<!--Give the smallest, complete command line that exhibits the problem.
If you are using libvirt, virsh, or vmm, you can likely find the QEMU
command line arguments in /var/log/libvirt/qemu/$GUEST.log.-->
```
qemu-system-riscv64 -nographic -semihosting -icount shift=1 -machine virt -cpu max,smpmpmt=false,pmu-mask=0xfffffff8,smdbltrp=true,ssdbltrp=true -bios rv64/ExceptionsHSm_ecall-00.elf
```
## Emulated/Virtualized environment
- Operating system:
<!--Windows 10 21H1, Fedora 37, etc.-->
- OS/kernel version:
<!--For POSIX guests, use `uname -a`.-->
- Architecture:
<!--x86, ARM, s390x, etc.-->
## Description of problem
Commit 18645f1957 ("target/riscv/csr.c: do not allow mstatus MPV/GVA writes") removed MPV and GVA from
the write masks of \`mstatus\` and \`mstatush\`. M-mode software can no longer set MPV, so an MRET with
MPP=S or U and MPV=1, the architectural way for M-mode to enter VS-mode or VU-mode, returns to HS-mode
or U-mode instead. MPRV-based guest accesses (MPRV=1, MPV=1) are impossible, and a GVA set by a trap
cannot be cleared. In the test, the M-mode handler sets MPP=S and MPV=1 (\`csrs mstatus\` with bit 39) and
executes \`mret\`. QEMU leaves MPV=0 and returns to HS-mode, so the next \`ecall\` is cause 9 (ecall from
HS) instead of cause 10 (ecall from VS). RV32 fails the same way through \`mstatush\` bit 7.
## Steps to reproduce
1.
2.
3.
## Additional information
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If using libvirt, libvirt logs and XML domain information may be relevant.-->
QEMU trace (RV64), from the T-SBI "go to VS-mode" handler to the \`ecall\` in the test:
\`\`\`
M 0x80000e20: csrrs x0,mstatus,x9 x7=0000000000001800 mstatus=8000040a00006e00
M 0x80000e24: addi x7,x0,128 x7=0000000000000080 mstatus=8000040a00006e00
M 0x80000e28: slli x7,x7,0x20 x7=0000008000000000 mstatus=8000040a00006e00
M 0x80000e2c: csrrs x0,mstatus,x7 x7=0000008000000000 mstatus=8000040a00006e00
M 0x80001bb0: mret x7=ab7fbb6fab7fbb6f mstatus=8000000a00006680
HS 0x80000070: addi x10,x0,6 x7=ab7fbb6fab7fbb6f mstatus=8000000a00006680
HS 0x80000074: ecall x7=ab7fbb6fab7fbb6f mstatus=8000040a00006e00
riscv_cpu_do_interrupt: hart:0, async:0, cause:0000000000000009, epc:0x80000074, tval:0x0000000000000000, desc=supervisor_ecall
\`\`\`
Expected, from Sail at the same point: \`csrs mstatus\` writes \`mstatus = 0x8000008A00006E00\` (MPV=1), mret
goes from M to VS, and the ecall traps with \`mcause = 0xA\` (RV32: \`mstatush = 0x80\`, same result).
Source (11.1.1): \`target/riscv/tcg/csr.c:2042-2045\`, the \`write_mstatus\` mask, and
\`target/riscv/tcg/csr.c:2108-2122\`, \`write_mstatush\`. Neither includes \`MSTATUS_MPV | MSTATUS_GVA\`.
Reverting 18645f1957 fixes it: add both fields to the masks when RVH is enabled.
issue
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