RISC-V IOMMU: fctl.BE is writable and retains 1 although the IOMMU supports a single endianness
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## Host environment
- Operating system:
Linux
- OS/kernel version:
Linux centos7 6.6.87.2-microsoft-standard-WSL2
- Architecture:
x86
- QEMU flavor:
qemu-system-riscv64
- QEMU version:
v11.0.0-1713-gde5d8bfd61\`, reported version 11.0.50
- QEMU command line:
<!--Give the smallest, complete command line that exhibits the problem.
</li>
</ul>
<p data-sourcepos="39:1-40:62">If you are using libvirt, virsh, or vmm, you can likely find the QEMU
command line arguments in /var/log/libvirt/qemu/$GUEST.log.--></p>
<pre data-sourcepos="42:3-50:5"><code>qemu-system-riscv64 \
-M virt,iommu-sys=on,aia=aplic-imsic \
-cpu rv64,smstateen=true \
-m 8G \
-nographic \
-device edu,dma_mask=0xFFFFFFFFFFFFFFFF \
-bios bin/iommu_fctl_be.elf
</code></pre>
<h2 id="user-content-emulatedvirtualized-environment" data-sourcepos="52:1-52:35">Emulated/Virtualized environment<a href="#emulatedvirtualized-environment" aria-label="Link to heading 'Emulated/Virtualized environment'" data-heading-content="Emulated/Virtualized environment" class="anchor"></a></h2>
<ul data-sourcepos="54:1-62:28">
<li data-sourcepos="54:1-56:41">
<p data-sourcepos="54:3-54:19">Operating system:</p>
<!--Windows 10 21H1, Fedora 37, etc.-->
- OS/kernel version:
<!--For POSIX guests, use `uname -a`.-->
- Architecture:
<!--x86, ARM, s390x, etc.-->
## Description of problem
capabilities.END reads 0, which means the IOMMU supports a single endianness (little-endian in this model). fctl.BE is a WARL field that selects the endianness of the IOMMU's implicit memory accesses. With a single supported endianness, fctl.BE reflects that endianness (0 for little-endian) and a write of an unsupported value must read back the legal value (0). The model lets software set fctl.BE to 1 and reads it back as 1, while still performing little-endian accesses.
## Steps to reproduce
1. [iommu_fctl_be.c](/uploads/6b8e20a41cd8a9692df0b9827e545bef/iommu_fctl_be.c)
2. Built with: `riscv64-unknown-elf-gcc -march=rv64gc -mabi=lp64 -mcmodel=medany -nostartfiles -nostdlib`
3. [iommu_fctl_be.elf](/uploads/84adb10abb5f2c38d25fa75d67c035a4/iommu_fctl_be.elf)
```
qemu-system-riscv64 \
-M virt,iommu-sys=on,aia=aplic-imsic \
-cpu rv64,smstateen=true \
-m 8G \
-nographic \
-device edu,dma_mask=0xFFFFFFFFFFFFFFFF \
-bios bin/iommu_fctl_be.elf
```
## Additional information
The guest program (`tests/iommu_fctl_be.c`):
1. Reads capabilities and confirms END (bit 27) is 0.
2. Reads fctl, writes fctl.BE (bit 0) = 1, and reads fctl back.
## Expected behaviour (per spec)
With capabilities.END = 0 the IOMMU supports one endianness and fctl.BE reflects that endianness; a write attempting the other endianness must read back the supported value (0).
Spec references:
- RISC-V IOMMU Architecture Specification, Section 6.3, capabilities.END (bit 27, read-only): "When 0, IOMMU supports one endianness (either little or big). When 1, IOMMU supports both endianness. The endianness is defined in the fctl register."
- RISC-V IOMMU Architecture Specification, Section 6.4, fctl.BE (WARL): "When 0, IOMMU accesses to memory resident data structures" are little-endian.
- RISC-V IOMMU Architecture Specification, software guidelines: "(supports only one endianness) and fctl.BE is 0 (i.e. little endian)."
## Observed behaviour
```
capabilities.END (bit 27) = 0x00000000
fctl before = 0x00000000
wrote fctl.BE=1, fctl after = 0x00000001 BE = 1
BUG: END=0 (little endianness) but fctl.BE accepted and read back 1.
```
## Source location
`hw/riscv/riscv-iommu.c`, register initialisation:
```c
stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL],
~(RISCV_IOMMU_FCTL_BE | RISCV_IOMMU_FCTL_WSI));
```
This makes fctl.BE writable. capabilities.END is never set (it reads 0), and the model always performs little-endian accesses; the comment at the SBE check in the same file states "CAP_END is always zero (only one endianess). FCTL_BE is always zero (little-endian accesses)". Despite that, fctl.BE accepts and retains the value 1.
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issue
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