RISC-V IOMMU: a command with a reserved bit set is processed instead of being reported as illegal
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## Host environment
- Operating system:
Linux
- OS/kernel version:
Linux centos7 6.6.87.2-microsoft-standard-WSL2
- Architecture:
x86
- QEMU flavor:
qemu-system-riscv64
- QEMU version:
v11.0.0-1713-gde5d8bfd61\`, reported version 11.0.50
- QEMU command line:
<!--Give the smallest, complete command line that exhibits the problem.
</li>
</ul>
<p data-sourcepos="39:1-40:62">If you are using libvirt, virsh, or vmm, you can likely find the QEMU
command line arguments in /var/log/libvirt/qemu/$GUEST.log.--></p>
<pre data-sourcepos="42:3-50:5"><code>qemu-system-riscv64 \
-M virt,iommu-sys=on,aia=aplic-imsic \
-cpu rv64,smstateen=true \
-m 8G \
-nographic \
-device edu,dma_mask=0xFFFFFFFFFFFFFFFF \
-bios bin/iommu_cmd_reserved_bit.elf
</code></pre>
<h2 id="user-content-emulatedvirtualized-environment" data-sourcepos="52:1-52:35">Emulated/Virtualized environment<a href="#emulatedvirtualized-environment" aria-label="Link to heading 'Emulated/Virtualized environment'" data-heading-content="Emulated/Virtualized environment" class="anchor"></a></h2>
<ul data-sourcepos="54:1-62:28">
<li data-sourcepos="54:1-56:41">
<p data-sourcepos="54:3-54:19">Operating system:</p>
<!--Windows 10 21H1, Fedora 37, etc.-->
- OS/kernel version:
<!--For POSIX guests, use `uname -a`.-->
- Architecture:
<!--x86, ARM, s390x, etc.-->
## Description of problem
The spec states that a command is illegal if a reserved bit in it is set to 1, and that the command queue must then set cqcsr.cmd_ill and stop processing. The model decodes commands only by opcode and func3 (and a few specific operand combinations); it does not check reserved bits. A command with a reserved bit set is accepted and processed, and cqcsr.cmd_ill is not set.
## Steps to reproduce
1. [iommu_cmd_reserved_bit.c](/uploads/7fd011671f91df7e72520d85aa182d76/iommu_cmd_reserved_bit.c)
2. Built with: `riscv64-unknown-elf-gcc -march=rv64gc -mabi=lp64 -mcmodel=medany -nostartfiles -nostdlib`
3. [iommu_cmd_reserved_bit.elf](/uploads/94fbe08ec36c8c366c92c01bf49b3d38/iommu_cmd_reserved_bit.elf)
```
qemu-system-riscv64 \
-M virt,iommu-sys=on,aia=aplic-imsic \
-cpu rv64,smstateen=true \
-m 8G \
-nographic \
-device edu,dma_mask=0xFFFFFFFFFFFFFFFF \
-bios iommu_cmd_reserved_bit.elf
```
## Additional information
The guest program (`tests/iommu_cmd_reserved_bit.c`):
1. Enables the IOMMU and the command queue.
2. Builds an IOFENCE.C command and sets a reserved bit (bit 14 of the first doubleword) to 1.
3. Places it in the command queue, advances cqt, and waits until either the queue drains or cqcsr.cmd_ill is set.
4. Reads cqcsr (cmd_ill is bit 10) and cqh.
## Expected behaviour (per spec)
The command queue must treat the command as illegal: set cqcsr.cmd_ill and stop processing (cqh does not advance past the illegal command).
Spec references:
- RISC-V IOMMU Architecture Specification, Command-Queue: "A command is determined to be illegal if it uses a reserved encoding or if a reserved bit is set to 1. ... If an illegal or unsupported command is fetched and decoded by the command-queue then the command-queue sets the cqcsr.cmd_ill bit and stops processing commands from the command-queue. To re-enable command processing software should clear the cmd_ill bit by writing 1 to it."
## Observed behaviour
```
Submitting IOFENCE.C with reserved bit 14 set (cmd.low = 0x0000000000004002)
cqcsr after = 0x00010003 cqh = 0x00000001 cqt = 0x00000001
cmd_ill (cqcsr bit 10) = 0
BUG: command with a reserved bit was processed; cmd_ill not set.
```
cqh advanced to cqt, so the command was processed; cqcsr.cmd_ill stayed 0.
## Source location
`hw/riscv/riscv-iommu.c`, `riscv_iommu_process_cq_tail()`. The command dispatch switches on the opcode/func3 pair and handles a few specific operand combinations (for example IOTINVAL.GVMA with PSCV=1, IODIR.INVAL_PDT with DV=0, an unknown opcode). It does not test the reserved bits of any command, so a command with a reserved bit set does not set cqcsr.cmd_ill and is processed normally.
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issue
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