RISC-V IOMMU: reserved bits in a basic-mode (M==3) MSI PTE are not checked
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## Host environment
- Operating system:
Linux x86_64
- OS/kernel version:
Linux centos7 6.6.87.2-microsoft-standard-WSL2
- Architecture:
x86
- QEMU flavor:
qemu-system-riscv64
- QEMU version:
v11.0.0-1713-gde5d8bfd61\`, reported version 11.0.50
- QEMU command line:
<!--Give the smallest, complete command line that exhibits the problem.
</li>
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<p data-sourcepos="39:1-40:62">If you are using libvirt, virsh, or vmm, you can likely find the QEMU
command line arguments in /var/log/libvirt/qemu/$GUEST.log.--></p>
<pre data-sourcepos="42:3-52:5"><code>qemu-system-riscv64 \
-M virt,iommu-sys=on,aia=aplic-imsic \
-cpu rv64,smstateen=true \
-m 8G \
-trace riscv_iommu_msi \
-trace riscv_iommu_flt \
-nographic \
-device edu,dma_mask=0xFFFFFFFFFFFFFFFF \
-bios bin/iommu_msi_pte_reserved.elf
</code></pre>
<h2 id="user-content-emulatedvirtualized-environment" data-sourcepos="54:1-54:35">Emulated/Virtualized environment<a href="#emulatedvirtualized-environment" aria-label="Link to heading 'Emulated/Virtualized environment'" data-heading-content="Emulated/Virtualized environment" class="anchor"></a></h2>
<ul data-sourcepos="56:1-64:28">
<li data-sourcepos="56:1-58:41">
<p data-sourcepos="56:3-56:19">Operating system:</p>
<!--Windows 10 21H1, Fedora 37, etc.-->
- OS/kernel version:
<!--For POSIX guests, use `uname -a`.-->
- Architecture:
<!--x86, ARM, s390x, etc.-->
## Description of problem
For an MSI PTE in basic (write-through) mode (`msipte.M == 3`), the spec requires that if any bit reserved for future standard use is set within the MSI PTE, the IOMMU stops and reports "MSI PTE misconfigured" (cause = 263). The model checks only the V and C bits, then uses the PPN and performs the write; it never checks the reserved fields, so a basic-mode MSI PTE with a reserved bit set is accepted and the MSI write proceeds with no fault.
## Steps to reproduce
1. [iommu_msi_pte_reserved.c](/uploads/1ca8bbf2165588326105de7807e9d0de/iommu_msi_pte_reserved.c)
2. Built with: `riscv64-unknown-elf-gcc -march=rv64gc -mabi=lp64 -mcmodel=medany -nostartfiles -nostdlib`
3. [iommu_msi_pte_reserved.elf](/uploads/51aad46351b278c200888e925b0e9354/iommu_msi_pte_reserved.elf)
```
qemu-system-riscv64 \
-M virt,iommu-sys=on,aia=aplic-imsic \
-cpu rv64,smstateen=true \
-m 8G \
-trace riscv_iommu_msi \
-trace riscv_iommu_flt \
-nographic \
-device edu,dma_mask=0xFFFFFFFFFFFFFFFF \
-bios bin/iommu_msi_pte_reserved.elf
```
## Additional information
The guest program (`tests/iommu_msi_pte_reserved.c`):
1. Registers a DC with MSI Flat mode and a basic-mode MSI PTE (M = 3) whose PPN points at a regular page-aligned buffer `msi_buf`.
2. Sets reserved bit 3 of the MSI PTE (between M\[2:1\] and PPN\[53:10\]); V, M, and PPN are otherwise valid.
3. Maps gva_msi to the MSI guest physical page and triggers the MSI.
## Expected behaviour (per spec)
The MSI translation should stop with CAUSE = 263 (MSI PTE misconfigured); no write should be performed.
Spec references:
- RISC-V IOMMU Architecture Specification, Section 3.3.3, MSI address translation, step 13: "If msipte.M == 3 the PTE is in basic translate mode and the translation process is as follows: a. If any bits or encoding that are reserved for future standard use are set within msipte, stop and report "MSI PTE misconfigured" (cause = 263)."
## Observed behaviour
```
MSI PTE[0] = 0x000000002002600F (reserved bit 00000003 set)
Result
MSI write landed (msi_buf[0]) : 0x00000001
Any fault logged : NO
BUG: reserved bit in basic MSI PTE was ignored; no CAUSE 263, write performed.
```
The reserved bit is ignored: the write completed (msi_buf\[0\] = MSI data) and no fault was logged.
## Source location
`hw/riscv/riscv-iommu.c`, `riscv_iommu_msi_write()`, basic-mode (`M == 3`) branch. After reading the MSI PTE the code checks only V and C, then proceeds directly to extract the PPN and perform the DMA write. The reserved fields in a basic-mode MSI PTE - bits \[9:3\] and \[62:54\] of the first doubleword and the entire second doubleword - are never validated.
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issue
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