RISC-V IOMMU: write through a first-stage leaf PTE with A=0 (D=1) is not faulted when SADE=0
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## Host environment
- Operating system:
Linux x86_84
- OS/kernel version:
Linux centos7 6.6.87.2-microsoft-standard-WSL2
- Architecture:
x86_84
- QEMU flavor:
qemu-system-riscv64
- QEMU version:
v11.0.0-1713-gde5d8bfd61\`, reported version 11.0.50
- QEMU command line:
<!--Give the smallest, complete command line that exhibits the problem.
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<p data-sourcepos="39:1-40:62">If you are using libvirt, virsh, or vmm, you can likely find the QEMU
command line arguments in /var/log/libvirt/qemu/$GUEST.log.--></p>
<pre data-sourcepos="42:3-51:5"><code>qemu-system-riscv64 \
-M virt,iommu-sys=on,aia=aplic-imsic \
-cpu rv64,smstateen=true \
-m 8G \
-trace riscv_iommu_dma \
-nographic \
-device edu,dma_mask=0xFFFFFFFFFFFFFFFF \
-bios bin/iommu_vs_pte_a0_sade0_write.elf
</code></pre>
<h2 id="user-content-emulatedvirtualized-environment" data-sourcepos="53:1-53:35">Emulated/Virtualized environment<a href="#emulatedvirtualized-environment" aria-label="Link to heading 'Emulated/Virtualized environment'" data-heading-content="Emulated/Virtualized environment" class="anchor"></a></h2>
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<p data-sourcepos="55:3-55:19">Operating system:</p>
<!--Windows 10 21H1, Fedora 37, etc.-->
- OS/kernel version:
Linux centos7 6.6.87.2-microsoft-standard-WSL2
- Architecture:
x86_64
## Description of problem
When DC.tc.SADE = 0 the IOMMU may not perform hardware update of the Accessed (A) bit for first-stage page tables. For a write access through a first-stage leaf PTE the Accessed bit must still be set; if it is 0 and hardware update is disabled, the access must raise a (first-stage) store/AMO page fault.
The model only checks the Dirty (D) bit on the write path. A write through a first-stage leaf PTE with A = 0 and D = 1 while SADE = 0 is not faulted: the Access-bit check is gated on read permission only. The translation completes and the DMA write proceeds.
## Steps to reproduce
1. [iommu_vs_pte_a0_sade0_write.c](/uploads/5b18dacceb8d539f8a0f97e665838f32/iommu_vs_pte_a0_sade0_write.c)
2. Built with: `riscv64-unknown-elf-gcc -march=rv64gc -mabi=lp64 -mcmodel=medany -nostartfiles -nostdlib`
3. [iommu_vs_pte_a0_sade0_write.elf](/uploads/9a494dbe2b6cc5eb2ef6b027a61f50e3/iommu_vs_pte_a0_sade0_write.elf)
````
```
qemu-system-riscv64 \
-M virt,iommu-sys=on,aia=aplic-imsic \
-cpu rv64,smstateen=true \
-m 8G \
-trace riscv_iommu_dma \
-nographic \
-device edu,dma_mask=0xFFFFFFFFFFFFFFFF \
-bios bin/iommu_vs_pte_a0_sade0_write.elf
```
````
## Additional information
The guest program (`tests/iommu_vs_pte_a0_sade0_write.c`):
1. Registers a DC with SADE = 0, GADE = 0 (G-stage Sv39x4, VS-stage Sv39).
2. Maps the destination buffer with a VS-stage leaf PTE of A = 0, D = 1. The G-stage PTE keeps A = 1, D = 1, so any first-stage fault is attributable to the VS-stage A = 0.
3. Issues an EDU -\> RAM DMA (a write to dst_buf through the A = 0 leaf PTE).
## Expected behaviour (per spec)
The write should raise a first-stage store/AMO page fault; no data should be written.
Spec reference:
- RISC-V IOMMU Architecture Specification, Section 3.1.3, Translation-control fields: "If SADE is 1, the IOMMU updates A and D bits in first-stage PTEs atomically. If SADE is 0, the IOMMU causes a page-fault corresponding to the original access type if the A bit is 0 or if the memory access is a store and the D bit is 0."
## Observed behaviour
```
DC.tc.SADE = 0x00000000
VS-stage dst leaf PTE built with A=0, D=1 at gva 0x200000
DMA: EDU internal buffer to RAM (GVA 0x200000) (write)
Result
Any fault logged (FQT != FQH) : NO
BUG: write through A=0 (D=1) leaf with SADE=0 did not fault.
The access-bit check is skipped on the write path.
```
QEMU trace: the write translates without fault:
```
riscv_iommu_dma translate 0000:01.0 #0 WR 0x200000 -> 0x80092000
```
(Total fault records in the run: 0.)
## Root cause
In `hw/riscv/riscv-iommu.c`, `riscv_iommu_spa_fetch()` (master commit de5d8bfd61, lines 483-485):
```c
} else if ((iotlb->perm & IOMMU_RO) && !ade && !(pte & PTE_A)) {
... /* fault: PTE.A == 0 */
} else if ((iotlb->perm & IOMMU_WO) && !ade && !(pte & PTE_D)) {
... /* fault: PTE.D == 0 */
}
```
The Access-bit check is conditioned on `iotlb->perm & IOMMU_RO`. A write-only access presents `IOMMU_WO` (read bit clear), so the A-bit check is skipped and only the Dirty bit is checked. When A = 0 and D = 1 neither branch fires, and the walk falls through to the leaf-complete case. Per the IOMMU spec (Section 3.1.3) the A == 0 condition must fault on any access type when SADE = 0.
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issue
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