sfence.w.inval and sfence.inval.ir does not raise illegal instruction exception when executed in U-Mode (#3493) · Issues · QEMU / QEMU · GitLab

sfence.w.inval and sfence.inval.ir does not raise illegal instruction exception when executed in U-Mode

## Host environment - QEMU flavor: ``` qemu-system-riscv32 ``` - QEMU version: ``` qemu-system-riscv32 v10.2.2 ``` - QEMU command line: ```shellscript qemu-system-riscv32 -nographic -semihosting -icount shift=1 -machine virt -cpu max,pmu-mask=0xfffffff8 -bios ``` ## Description Accessing sfence.w.inval and sfence.ir.inval in U-Mode does not raise illegal instruction exception. According to chapter 15 of the Priv ISA spec > Attempting to execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U-mode raises an illegal-instruction exception. ## Attachments [rv32_Svinval.elf](/uploads/9080e83543010e85b7b9b045dc0b6a0e/rv32_Svinval.elf) [rv32_Svinval.objdump](/uploads/e5af0b78485f7e754e90ca9cbe50c38f/rv32_Svinval.objdump) [rv32_Svinval.trace.log](/uploads/9138336a554db41cbd45c6d99819bce6/rv32_Svinval.trace.log)

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