mstatus.UXL is writable with reserved value 11
## Host environment - Operating system: <!--Windows 10 21H1, Fedora 37, etc.--> - OS/kernel version: 5.14.0-611.30.1.el9_7.x86_64 #1 SMP PREEMPT_DYNAMIC Wed Feb 11 06:42:00 EST 2026 x86_64 x86_64 x86_64 GNU/Linux - Architecture: x86 - QEMU flavor: qemu-system-riscv64 - QEMU version: v10.2.2 - QEMU command line: <!--Give the smallest, complete command line that exhibits the problem. If you are using libvirt, virsh, or vmm, you can likely find the QEMU command line arguments in /var/log/libvirt/qemu/$GUEST.log.--> ``` qemu-system-riscv64 -nographic -semihosting -icount shift=1 -machine virt -cpu max,pmu-mask=0xfffffff8 -bios /home/harris/cvw/addins/riscv-arch-test-dh/work/qemu-rv64-max/elfs/priv/Sm/Sm-00.elf ``` ## Emulated/Virtualized environment - Operating system: bare metal - OS/kernel version: <!--For POSIX guests, use `uname -a`.--> - Architecture: <!--x86, ARM, s390x, etc.--> ## Description of problem Writing all 1s to mstatus gives 0x800002cb00fe7faa. In particular, bits 33:32 (mstatus.UXL) are 11. This is a reserved value that should not be able to go in this field. Moreover, it violates the rule that UXLEN \<= SXLEN. Note that mstatus.SXL is correctly set to 10. This test is part of riscv-arch-test. The error printed is ``` RVCP-SUMMARY: TEST FAILED - Test File "Sm-00.S" RVCP: DEBUG INFORMATION FOLLOWS RVCP: Test Info: "test: 244; cg: Sm_mcsr_cg; cp: cp_mcsr_access; bin: mstatus_csrrw1" RVCP: Instruction: 0x300e9073 RVCP: Approximate address (failure may be slightly after this): 0x0000000080004324 RVCP: Register: x30 RVCP: Bad Value: 0x800002cb00fe7faa RVCP: Expected Value: 0x8000020a00fe7faa RVCP: END OF DEBUG INFORMATION ``` Per Section 3.1.6.3 of the riscv-privileged-20260120: ``` For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively.  If S-mode is implemented, the set of legal values that the UXL field may assume excludes those that would cause UXLEN to be greater than SXLEN. ``` ## Steps to reproduce 1. qemu-system-riscv64 -nographic -semihosting -icount shift=1 -machine virt -cpu max,pmu-mask=0xfffffff8 -bios /home/harris/cvw/addins/riscv-arch-test-dh/work/qemu-rv64-max/elfs/priv/Sm/Sm-00.elf 2. 3. ## Additional information <!--Attach logs, stack traces, screenshots, etc. Compress the files if necessary. If using libvirt, libvirt logs and XML domain information may be relevant.--> [Sm-00.elf.zip](/uploads/56e6999ebfe39da8bc3c62a0e8d290ca/Sm-00.elf.zip) <!--The line below ensures that proper tags are added to the issue. Please do not remove it.-->
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