<!-- This is the upstream QEMU issue tracker. If you are able to, it will greatly facilitate bug triage if you attempt to reproduce the problem with the latest qemu.git master built from source. See https://www.qemu.org/download/#source for instructions on how to do this. QEMU generally supports the last two releases advertised on https://www.qemu.org/. Problems with distro-packaged versions of QEMU older than this should be reported to the distribution instead. See https://www.qemu.org/contribute/report-a-bug/ for additional guidance. If this is a security issue, please consult https://www.qemu.org/contribute/security-process/ --> ## Host environment - Operating system: Ubuntu 22.04.5 LTS <!-- Windows 10 21H1, Fedora 37, etc. --> - OS/kernel version: 6.8.0-79-generic <!-- For POSIX hosts, use `uname -a` --> - Architecture: x86 <!-- x86, ARM, s390x, etc. --> - QEMU flavor: qemu-system-riscv64 <!-- qemu-system-x86_64, qemu-aarch64, qemu-img, etc. --> - QEMU version: 10.1.0 (commit f8b2f64) <!-- e.g. `qemu-system-x86_64 --version` --> - QEMU command line: <!-- Give the smallest, complete command line that exhibits the problem. If you are using libvirt, virsh, or vmm, you can likely find the QEMU command line arguments in /var/log/libvirt/qemu/$GUEST.log. --> ``` ./qemu-system-riscv64 -nographic \ -machine virt \ -cpu rv64,g=on,c=on,h=on\ -m 512M \ -bios none \ -kernel "build/qemu/rvh_test.bin" ``` ## Emulated/Virtualized environment - Operating system: - (baremetal) - OS/kernel version: - (baremetal) - Architecture: RISC-V (riscv64-softmmu) ## Description of problem I am executing tests for the riscv hypervisor extension from `https://github.com/josecm/riscv-hyp-tests`. In particular, test `vsie` in the `check_xip_regs` category fails. Following is the analysis of what the test is checking, what the test expects and what QEMU does. **What the test checks** The test checks how the VS-mode Interrupt Enable (vsie) register is returned. For this, the test sets the 64 bits of the registers and, after that, reads it contents. **What the test expects** The test expects that bits 1 (SSIP), 5 (STIP) and 9 (SEIP) are set, while the rest are all cleared. **What QEMU does** QEMU also sets bit 14 and 15 in the `vsie` register. **Comments** Bit 14 and 15 must be 0 following the description of the `vsie` register in the Supervisor-level ISA 1.12. ## Steps to reproduce Assuming a `riscv64-unknown-elf-` cross compiler is installed in the machine: 1. `git clone https://github.com/josecm/riscv-hyp-tests.git` 2. `cd riscv-hyp-tests` 3. `LOG_LEVEL=LOG_VERBOSE PLAT=qemu make` 4. Execute the previous command line. ## Additional information Example output: ``` ... VERBOSE: setting mideleg and hideleg ... vsie FAILED (ffffffffffffffff ffffffffffffc222 0000000000000222) ... ``` <!-- The line below ensures that proper tags are added to the issue. Please do not remove it. -->