RISC-V: Cannot set SEIP bit of mip csr register in M mode
Host environment
- Operating system: Ubuntu
- OS/kernel version: 5.13.0-30-generic #33~20.04.1-Ubuntu SMP Mon Feb 7 14:25:10 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux
- Architecture: x86_64
- QEMU flavor: riscv64-softmmu,riscv32-softmmu
- QEMU version: 6.1.1
- QEMU command line:
qemu-system-riscv64 -smp 2 -M virt -bios none -nographic -device loader,file=./testfile.bin,addr=0x80000000
Emulated/Virtualized environment
- Operating system: No operating system
- OS/kernel version: None
- Architecture: riscv64 imafc, riscv32 imafc
Description of problem
Steps to reproduce
- run assembly instructions in M mode:
not t0, x0 // set t0 to 0b11..11
csrs mip, t0 // write mip with t0, mip registers are WARL(Write Any Values, Reads Legal Values)
csrr t1, mip // read value from mip to t1
- GDB enters the command
display/z $t1
to see that the content of the t1 register is 0x466, which means that the SEIP bit of mip is not set. - According to page 47 of riscv-privileged-20211203,
SEIP is writable in mip
. - According to page 81 of the same manual,
If implemented, SEIP is read-only in sip
. - However, the above code and results show that the SEIP bit of mip cannot be set by software in M mode.
Additional information
Edited by LiuJiLan