intel-hda: stream reset bits are broken
I hope I have understood the system correctly. It seems "[Bug 1905226] Re: intel-hda: stream reset bits are broken" has not been carried over correctly from the old bugtracker but should have been. It is still valid, I have just hit it myself and the code referred to in the original report is still as shown (and I have ofc searched for and not found it here).
Launchpad Bug Tracker Fri, 09 Jul 2021 21:32:54 -0700
https://bugs.launchpad.net/bugs/1905226
Title: intel-hda: stream reset bits are broken
Bug description: From HD audio spec, section 3.3.35:
"Stream Reset (SRST): Writing a 1 causes the corresponding stream to be reset. [...] After the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. Software must read a 1 from this bit to verify that the stream is in reset. Writing a 0 causes the corresponding stream to exit reset. When the stream hardware is ready to begin operation, it will report a 0 in this bit. Software must read a 0 from this bit before accessing any of the stream registers."
So to reset a stream I set the bit, but it never reads back as 1 so the driver either times out or will hang forever waiting for it to become 1. I looked into why this happens and found that as of the latest version (8110fa1d), in function intel_hda_set_st_ctl() of the https://github.com/qemu/qemu/blob/master/hw/audio/intel-hda.c,
if (st->ctl & 0x01) {
/* reset */
dprint(d, 1, "st #%d: reset\n", reg->stream);
st->ctl = SD_STS_FIFO_READY << 24;
}
This causes the bit to immediately become set to 0 even if I write a 1, and clearly does not meet the spec. I checked behaviour of real hardware and it works as expected, i.e. I see the bit will become 1 and 0 when I write to it.