6.1.0 introduces regression in q35, unable to add more than 15 pcie-root-ports

Run the following QEMU command line:

qemu-system-x86_64 -M q35 -nodefaults \
-device pcie-root-port,port=0x10,chassis=1,id=pci.1,bus=pcie.0,multifunction=on,addr=0x2 \
-device VGA,bus=pci.1 \
-device pcie-root-port,port=0x11,chassis=2,id=pci.2,bus=pcie.0,addr=0x2.0x1 \
-device pcie-root-port,port=0x12,chassis=3,id=pci.3,bus=pcie.0,addr=0x2.0x2 \
-device pcie-root-port,port=0x13,chassis=5,id=pci.5,bus=pcie.0,addr=0x2.0x3 \
-device pcie-root-port,port=0x14,chassis=6,id=pci.6,bus=pcie.0,addr=0x2.0x4 \
-device pcie-root-port,port=0x15,chassis=7,id=pci.7,bus=pcie.0,addr=0x2.0x5 \
-device pcie-root-port,port=0x16,chassis=8,id=pci.8,bus=pcie.0,addr=0x2.0x6 \
-device pcie-root-port,port=0x17,chassis=9,id=pci.9,bus=pcie.0,addr=0x2.0x7 \
-device pcie-root-port,port=0x18,chassis=10,id=pci.10,bus=pcie.0,multifunction=on,addr=0x3 \
-device pcie-root-port,port=0x19,chassis=11,id=pci.11,bus=pcie.0,addr=0x3.0x1 \
-device pcie-root-port,port=0x1a,chassis=12,id=pci.12,bus=pcie.0,addr=0x3.0x2 \
-device pcie-root-port,port=0x1b,chassis=13,id=pci.13,bus=pcie.0,addr=0x3.0x3 \
-device pcie-root-port,port=0x1c,chassis=14,id=pci.14,bus=pcie.0,addr=0x3.0x4 \
-device pcie-root-port,port=0x1d,chassis=15,id=pci.15,bus=pcie.0,addr=0x3.0x5 \
-device pcie-root-port,port=0x1e,chassis=16,id=pci.16,bus=pcie.0,addr=0x3.0x6 

Since QEMU 6.1.0 this no longer gets out of the BIOS, with the QEMU display showing

Guest has not initialized the display (yet)

Enabling the SeaBIOS debug console using -chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios

SeaBIOS (version rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org)
BUILD: gcc: (GCC) 4.8.5 20150623 (Red Hat 4.8.5-39) binutils: version 2.27-43.base.el7_8.1
No Xen hypervisor found.
Running on QEMU (q35)
Found QEMU fw_cfg
QEMU fw_cfg DMA interface supported
qemu/e820: addr 0x0000000000000000 len 0x0000000008000000 [RAM]
Relocating init from 0x000d4bf0 to 0x07fa9460 (size 92944)
Moving pm_base to 0x600
=== PCI bus & bridge init ===
PCI: pci_bios_init_bus_rec bus = 0x0
PCI: pci_bios_init_bus_rec bdf = 0x10
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x1
PCI: pci_bios_init_bus_rec bus = 0x1
PCI: subordinate bus = 0x0 -> 0x1
PCI: pci_bios_init_bus_rec bdf = 0x11
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x2
PCI: pci_bios_init_bus_rec bus = 0x2
PCI: subordinate bus = 0x0 -> 0x2
PCI: pci_bios_init_bus_rec bdf = 0x12
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x3
PCI: pci_bios_init_bus_rec bus = 0x3
PCI: subordinate bus = 0x0 -> 0x3
PCI: pci_bios_init_bus_rec bdf = 0x13
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x4
PCI: pci_bios_init_bus_rec bus = 0x4
PCI: subordinate bus = 0x0 -> 0x4
PCI: pci_bios_init_bus_rec bdf = 0x14
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x5
PCI: pci_bios_init_bus_rec bus = 0x5
PCI: subordinate bus = 0x0 -> 0x5
PCI: pci_bios_init_bus_rec bdf = 0x15
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x6
PCI: pci_bios_init_bus_rec bus = 0x6
PCI: subordinate bus = 0x0 -> 0x6
PCI: pci_bios_init_bus_rec bdf = 0x16
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x7
PCI: pci_bios_init_bus_rec bus = 0x7
PCI: subordinate bus = 0x0 -> 0x7
PCI: pci_bios_init_bus_rec bdf = 0x17
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x8
PCI: pci_bios_init_bus_rec bus = 0x8
PCI: subordinate bus = 0x0 -> 0x8
PCI: pci_bios_init_bus_rec bdf = 0x18
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0x9
PCI: pci_bios_init_bus_rec bus = 0x9
PCI: subordinate bus = 0x0 -> 0x9
PCI: pci_bios_init_bus_rec bdf = 0x19
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0xa
PCI: pci_bios_init_bus_rec bus = 0xa
PCI: subordinate bus = 0x0 -> 0xa
PCI: pci_bios_init_bus_rec bdf = 0x1a
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0xb
PCI: pci_bios_init_bus_rec bus = 0xb
PCI: subordinate bus = 0x0 -> 0xb
PCI: pci_bios_init_bus_rec bdf = 0x1b
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0xc
PCI: pci_bios_init_bus_rec bus = 0xc
PCI: subordinate bus = 0x0 -> 0xc
PCI: pci_bios_init_bus_rec bdf = 0x1c
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0xd
PCI: pci_bios_init_bus_rec bus = 0xd
PCI: subordinate bus = 0x0 -> 0xd
PCI: pci_bios_init_bus_rec bdf = 0x1d
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0xe
PCI: pci_bios_init_bus_rec bus = 0xe
PCI: subordinate bus = 0x0 -> 0xe
PCI: pci_bios_init_bus_rec bdf = 0x1e
PCI: primary bus = 0x0
PCI: secondary bus = 0xff -> 0xf
PCI: pci_bios_init_bus_rec bus = 0xf
PCI: subordinate bus = 0x0 -> 0xf
=== PCI device probing ===
Found 20 PCI devices (max PCI bus is 0f)
PCIe: using q35 mmconfig at 0xb0000000
=== PCI new allocation pass #1 ===
PCI: check devices
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 15 size 00001000 type io
PCI: secondary bus 15 size 00200000 type mem
PCI: secondary bus 15 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 14 size 00001000 type io
PCI: secondary bus 14 size 00200000 type mem
PCI: secondary bus 14 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 13 size 00001000 type io
PCI: secondary bus 13 size 00200000 type mem
PCI: secondary bus 13 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 12 size 00001000 type io
PCI: secondary bus 12 size 00200000 type mem
PCI: secondary bus 12 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 11 size 00001000 type io
PCI: secondary bus 11 size 00200000 type mem
PCI: secondary bus 11 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 10 size 00001000 type io
PCI: secondary bus 10 size 00200000 type mem
PCI: secondary bus 10 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 9 size 00001000 type io
PCI: secondary bus 9 size 00200000 type mem
PCI: secondary bus 9 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 8 size 00001000 type io
PCI: secondary bus 8 size 00200000 type mem
PCI: secondary bus 8 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 7 size 00001000 type io
PCI: secondary bus 7 size 00200000 type mem
PCI: secondary bus 7 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 6 size 00001000 type io
PCI: secondary bus 6 size 00200000 type mem
PCI: secondary bus 6 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 5 size 00001000 type io
PCI: secondary bus 5 size 00200000 type mem
PCI: secondary bus 5 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 4 size 00001000 type io
PCI: secondary bus 4 size 00200000 type mem
PCI: secondary bus 4 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 3 size 00001000 type io
PCI: secondary bus 3 size 00200000 type mem
PCI: secondary bus 3 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 2 size 00001000 type io
PCI: secondary bus 2 size 00200000 type mem
PCI: secondary bus 2 size 00200000 type prefmem
PCI: QEMU resource reserve cap: size 00001000 type io
PCI: secondary bus 1 size 00001000 type io
PCI: secondary bus 1 size 00200000 type mem
PCI: secondary bus 1 size 01000000 type prefmem
=== PCI new allocation pass #2 ===
PCI: out of I/O address space

Investigating changes in QEMU 6.1.0 I found the PCI hotplug change. Adding

 -global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off

Makes it successfully get out of the BIOS.

With QEMU < 6.1.0, I was able to successfully add 80+ pcie-root-ports without trouble before I got bored adding more.

So this switch to ACPI hotplug is a significant regression in ability to add PCI devices to QEMU