faults due to a amo instruction result in load faults instead of store/amo faults
In qemu-system-riscv64 6.0.0, when an atomic memory operation results in a page or access fault, it is reported as a load acess or page fault in the cause register (be it mcause or scause). However, it should be reported as a store/amo acces or page fault.
I'd guess because of the read-modify-write nature of these instructions, TCG probably first issues a load operation that will fail, and thus the load fault is raised. I might be off though, I'm not that familiar with qemu internals.
I'd be glad to submit a patch fixing it, but I really don't know how or what is the best way to transmit the information that the load is related to an amo instruction from the decode phase up to raise_mmu_exception. Should I just read the instruction and check the opcode at that point? Any better alternatives?