QEMU does not implement the 'LMUL ≥ SEW_MIN/ELEN' constraint for RISC-V Vector extenson

For the following constraints mentioned in Section 3.4.2 of the riscv-v-spec-1.0,

For a given supported fractional LMUL setting, implementations must support SEW settings between SEWMIN and LMUL * ELEN, inclusive.

however, in QEMU's target/riscv/vector_helper.c, what is implemented is VLEN * LMUL >= SEW,

target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
                            target_ulong s2, target_ulong x0)
{
    int vlmax, vl;
    RISCVCPU *cpu = env_archcpu(env);
    uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL);
    uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW);
    uint16_t sew = 8 << vsew;
    uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
    int xlen = riscv_cpu_xlen(env);
    bool vill = (s2 >> (xlen - 1)) & 0x1;
    target_ulong reserved = s2 &
                            MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                            xlen - 1 - R_VTYPE_RESERVED_SHIFT);
    uint16_t vlen = cpu->cfg.vlenb << 3;
    int8_t lmul;

    if (vlmul & 4) {
        /*
         * Fractional LMUL, check:
         *
         * VLEN * LMUL >= SEW
         * VLEN >> (8 - lmul) >= sew
         * (vlenb << 3) >> (8 - lmul) >= sew
         */
        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
            vill = true;
        }
    }

...
}